丝印代码：85411AIL；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

丝印代码：85411AIL；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

丝印代码：85411ALF；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

丝印代码：85411ALF；Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

丝印代码：85411AIL；Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes Page：15 Pages

丝印代码：85411AIL；Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：228.99 Kbytes Page：15 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER 1:2 650MHZ 8SOIC 集成电路（IC） 时钟缓冲器，驱动器

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK BUFFER 1:2 650MHZ 8SOIC 集成电路（IC） 时钟缓冲器，驱动器

丝印代码：85411ALF；Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：230.58 Kbytes Page：15 Pages

Low Skew, 1-to-2 Differential-to-LVDS Fanout Buffer

FEATURES • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor

Low Skew, 1-to-2 Different ial-to-LVDS Fanout Buffer

文件：230.58 Kbytes Page：15 Pages