2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

丝印代码：1BIL；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

丝印代码：1BIL；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

Low Skew,1-to-2,Differential-to-2.5V,3.3V LVPECL/ECL Fanout Buffer

The 853S011BI is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The 853S011BI is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 853S011BI ideal for those clock distribution Two differential 2.5V, 3.3V LVPECL/ECL outputs\nOne differential PCLK, nPCLK input pair\nPCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL\nMaximum output frequency: >2.5GHz\nTranslates any single-ended input signal to 3.3V LVPECL levels with resistor bias;

丝印代码：3S011BIL；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

丝印代码：3S011BIL；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

丝印代码：ICS3S012AIL；12:1, Differential-to-3.3V, 2.5V LVPECL Clock/Data Multiplexer

Features • High speed 12:1 differential multiplexer • One differential 3.3V or 2.5V LVPECL output • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 3.2GHz • Translates a

丝印代码：ICS3S012AIL；12:1, Differential-to-3.3V, 2.5V LVPECL Clock/Data Multiplexer

Features • High speed 12:1 differential multiplexer • One differential 3.3V or 2.5V LVPECL output • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 3.2GHz • Translates a

12:1 Differential-to-3.3V,2.5V LVPECL Clock/Data Multiplexer

The 853S012I is an 12:1 Differential-to-3.3V or 2.5V LVPECL Clock/Data Multiplexer which can operate up to 3.2GHz. The 853S012I has twelve differential selectable clock inputs. The CLK, nCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation de High speed 12:1 differential multiplexer\nOne differential 3.3V or 2.5V LVPECL output\nTwelve selectable differential clock or data inputs\nCLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML\nMaximum output frequency: 3.2GHz\nTranslates any single ended input sig;

Low Skew,Dual,1-to-3,Differential-to-2.5V,3.3V LVPECL/ECL Fanout Buffer

The 853S013I is a low skew, high performance dual 1-to-3 Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer. The 853S013I operates with a positive or negative power supply at 2.5V or 3.3V. Guaranteed output and part-to-part skew characteristics make the 853S013I ideal for those clock distribution ·Two differential LVPECL/ECL bank outputs\n·Two differential LVPECL clock input pairs\n·PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL\n·Output frequency: 2GHz (maximum)\n·Translates any single-ended input signal to LVPECL levels with resistor bias on;

丝印代码：53S01AIL；2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

丝印代码：53S01AIL；2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

丝印代码：3S1A；2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

丝印代码：3S1A；2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

丝印代码：ICS53S031BIL；Low Skew, 1-to-9, Differential-to-3.3V, 2.5V LVPECL/ECL Fanout Buffer

Features • Nine differential 2.5V, 3.3V LVPECL/ECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • PCLK, nPCLK supports the following input types: LVPECL, LVDS, CML, SST

丝印代码：ICS53S031BIL；Low Skew, 1-to-9, Differential-to-3.3V, 2.5V LVPECL/ECL Fanout Buffer

Features • Nine differential 2.5V, 3.3V LVPECL/ECL outputs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • PCLK, nPCLK supports the following input types: LVPECL, LVDS, CML, SST

4:1, Differential-To-3.3V, 2.5V LVPECL/ECL Clock Data Multiplexer

Features • High speed 4:1 differential multiplexer • One differential 3.3V, 2.5V LVPECL/ECL output • Four differential CLKx, nCLKx input pairs • Differential CLKx, nCLKx pairs can accept the following interface levels: LVPECL, LVDS, CML, SSTL • Maximum input/output frequency: 3GHz • Additiv

丝印代码：ICS53S057AIL；4:1, Differential-To-3.3V, 2.5V LVPECL/ECL Clock Data Multiplexer

Features • High speed 4:1 differential multiplexer • One differential 3.3V, 2.5V LVPECL/ECL output • Four differential CLKx, nCLKx input pairs • Differential CLKx, nCLKx pairs can accept the following interface levels: LVPECL, LVDS, CML, SSTL • Maximum input/output frequency: 3GHz • Additiv

丝印代码：ICS53S057AIL；4:1, Differential-To-3.3V, 2.5V LVPECL/ECL Clock Data Multiplexer

Features • High speed 4:1 differential multiplexer • One differential 3.3V, 2.5V LVPECL/ECL output • Four differential CLKx, nCLKx input pairs • Differential CLKx, nCLKx pairs can accept the following interface levels: LVPECL, LVDS, CML, SSTL • Maximum input/output frequency: 3GHz • Additiv

8:1 Differential-to-3.3V or 2.5V LVPECL/ECL Clock Multiplexer

Features • High speed 8:1 differential muliplexer • One differential 3.3V or 2.5V LVPECL output pair • Eight selectable differential PCLKx, nPCLKx input pairs • Differential PCLKx, nPCLKx pairs can accept the following interface levels: LVPECL, LVDS, SSTL,CML • Maximum output frequency: 2.5G

丝印代码：ICS853S058AIL；8:1 Differential-to-3.3V or 2.5V LVPECL/ECL Clock Multiplexer

Features • High speed 8:1 differential muliplexer • One differential 3.3V or 2.5V LVPECL output pair • Eight selectable differential PCLKx, nPCLKx input pairs • Differential PCLKx, nPCLKx pairs can accept the following interface levels: LVPECL, LVDS, SSTL,CML • Maximum output frequency: 2.5G

丝印代码：ICS853S058AIL；8:1 Differential-to-3.3V or 2.5V LVPECL/ECL Clock Multiplexer

Features • High speed 8:1 differential muliplexer • One differential 3.3V or 2.5V LVPECL output pair • Eight selectable differential PCLKx, nPCLKx input pairs • Differential PCLKx, nPCLKx pairs can accept the following interface levels: LVPECL, LVDS, SSTL,CML • Maximum output frequency: 2.5G

Skew, 1-to-10, Differential-to-LVPECL/ECL Fanout Buffer

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS53S111AIL；Skew, 1-to-10, Differential-to-LVPECL/ECL Fanout Buffer

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS53S111AIL；Skew, 1-to-10, Differential-to-LVPECL/ECL Fanout Buffer

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS53S111AIL；Skew, 1-to-10, Differential-to-LVPECL/ECL Fanout Buffer

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS53S111AIL；Skew, 1-to-10, Differential-to-LVPECL/ECL Fanout Buffer

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS3S111BIL；Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS3S111BIL；Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS3S111BIL；Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS3S111BIL；Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS53S111BIL；Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS53S111BIL；Low Skew, 1-to-10, Differential-to-2.5V, 3.3V LVPECL/ECL

Features • Ten differential 2.5V, 3.3V LVPECL/ECL outputs • Two selectable differential input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, SSTL, CML • Maximum output frequency: 2.5GHz • Translates any single-ended input signal to 3.3V LVPECL l

丝印代码：ICS53S12AIL；LOW SKEW, 1-TO-12, DIFFERENTIAL-TO- 3.3V, 2.5V LVPECL FANOUT BUFFER

FEATURES • Twelve differential 3.3V, 2.5V LVPECL outputs • PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL • Maximum output frequency: 1.5GHz • Translates any single-ended input signal to 2.5V or 3.3V LVPECL levels with a resis

丝印代码：ICS53S12AIL；LOW SKEW, 1-TO-12, DIFFERENTIAL-TO- 3.3V, 2.5V LVPECL FANOUT BUFFER

FEATURES • Twelve differential 3.3V, 2.5V LVPECL outputs • PCLK, nPCLK input pair • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL • Maximum output frequency: 1.5GHz • Translates any single-ended input signal to 2.5V or 3.3V LVPECL levels with a resis

12:2, Differential-to-3.3V, 2.5V LVPECL Multiplexer

Features • High speed 12.2 differential multiplexer • Two differential 3.3V or 2.5V LVPECL outputs • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS • Maximum output frequency: 3GHz • Translates any sin

丝印代码：ICS53S202AIL；12:2, Differential-to-3.3V, 2.5V LVPECL Multiplexer

Features • High speed 12.2 differential multiplexer • Two differential 3.3V or 2.5V LVPECL outputs • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS • Maximum output frequency: 3GHz • Translates any sin

丝印代码：ICS53S202AIL；12:2, Differential-to-3.3V, 2.5V LVPECL Multiplexer

Features • High speed 12.2 differential multiplexer • Two differential 3.3V or 2.5V LVPECL outputs • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS • Maximum output frequency: 3GHz • Translates any sin

丝印代码：3A01；Dual 2:1, 1:2 Differential-to-LVPECL/ ECL Multiplexer

Features • Dual 2:1, 1:2 MUX • Three LVPECL output pairs • Three differential clock inputs can accept: LVPECL, LVDS, CML • Loopback test mode available • Maximum output frequency: 2.5GHz • Propagation delay: 550ps (maximum) • Part-to-part skew: 275ps (maximum) • Additive phase jitter, RMS:

丝印代码：3A01；Dual 2:1, 1:2 Differential-to-LVPECL/ ECL Multiplexer

Features • Dual 2:1, 1:2 MUX • Three LVPECL output pairs • Three differential clock inputs can accept: LVPECL, LVDS, CML • Loopback test mode available • Maximum output frequency: 2.5GHz • Propagation delay: 550ps (maximum) • Part-to-part skew: 275ps (maximum) • Additive phase jitter, RMS:

丝印代码：S54A；Dual 2:1, 1:2 Differential-to-LVPECL/ECL Multiplexer

Features • Three differential LVPECL output pairs • Three differential LVPECL clock inputs • PCLKx/nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 2.5GHz • Part-to-part skew: 200ps (maximum) • Propagation delay: QA, nQA: 450ps (

丝印代码：S54A；Dual 2:1, 1:2 Differential-to-LVPECL/ECL Multiplexer

Features • Three differential LVPECL output pairs • Three differential LVPECL clock inputs • PCLKx/nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 2.5GHz • Part-to-part skew: 200ps (maximum) • Propagation delay: QA, nQA: 450ps (

Dual 2:1, 1:2 Differential-to-LVPECL/ ECL Multiplexer

Features • Dual 2:1, 1:2 MUX • Three LVPECL output pairs • Three differential clock inputs can accept: LVPECL, LVDS, CML • Loopback test mode available • Maximum output frequency: 2.5GHz • Propagation delay: 550ps (maximum) • Part-to-part skew: 275ps (maximum) • Additive phase jitter, RMS:

Low Skew, 1-to-4, Differential-to-2.5V, 3.3V LVPECL Fanout Buffer

文件：278.38 Kbytes Page：20 Pages

Low Skew, 1-to-4, Differential-to-2.5V, 3.3V LVPECL Fanout Buffer

文件：278.38 Kbytes Page：20 Pages

Low Skew, 1-to-4, Differential-to-2.5V, 3.3V LVPECL Fanout Buffer

文件：278.38 Kbytes Page：20 Pages

Low Skew, 1-to-4, Differential-to-2.5V, 3.3V LVPECL Fanout Buffer

文件：278.38 Kbytes Page：20 Pages

包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLOCK MANANGEMENT 集成电路（IC） 时钟缓冲器，驱动器

Low Skew, 1-to-4, Differential-to-2.5V, 3.3V LVPECL Fanout Buffer

文件：278.38 Kbytes Page：20 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER 1:6 2GHZ 20TSSOP 集成电路（IC） 时钟缓冲器，驱动器

2:1 Differential-to-LVPECL Multiplexer

文件：435.13 Kbytes Page：23 Pages

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

文件：601.31 Kbytes Page：20 Pages

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

文件：601.31 Kbytes Page：20 Pages

丝印代码：1BIL；LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

丝印代码：1BIL；LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

文件：601.31 Kbytes Page：20 Pages

LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages