2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

2:1 Differential-to-LVPECL Multiplexer

文件：435.13 Kbytes Page：23 Pages

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

丝印代码：1BIL；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

丝印代码：1BIL；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

丝印代码：3S011BIL；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

丝印代码：3S011BIL；Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

Features • Two differential 2.5V, 3.3V LVPECL/ECL outputs • One differential PCLK, nPCLK input pair • PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: >2.5GHz • Translates any single-ended input signal to 3.3V LVPECL le

Low Skew,1-to-2,Differential-to-2.5V,3.3V LVPECL/ECL Fanout Buffer

The 853S011CI is a low skew, high performance 1-to-2 Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The 853S011CI is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the 853S011CI ideal for those clock distribution • Two differential 2.5V, 3.3V LVPECL/ECL outputs\n• PCLK, nPCLK pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL\n• Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nPCLK input\n• Part-to-part skew: 150ps (maximum)\n• LVPECL mode o;

丝印代码：ICS3S012AIL；12:1, Differential-to-3.3V, 2.5V LVPECL Clock/Data Multiplexer

Features • High speed 12:1 differential multiplexer • One differential 3.3V or 2.5V LVPECL output • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 3.2GHz • Translates a

丝印代码：ICS3S012AIL；12:1, Differential-to-3.3V, 2.5V LVPECL Clock/Data Multiplexer

Features • High speed 12:1 differential multiplexer • One differential 3.3V or 2.5V LVPECL output • Twelve selectable differential clock or data inputs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Maximum output frequency: 3.2GHz • Translates a

12:1 Differential-to-3.3V,2.5V LVPECL Clock/Data Multiplexer

The 853S012I is an 12:1 Differential-to-3.3V or 2.5V LVPECL Clock/Data Multiplexer which can operate up to 3.2GHz. The 853S012I has twelve differential selectable clock inputs. The CLK, nCLK input pairs can accept LVPECL, LVDS or CML levels. The fully differential architecture and low propagation de High speed 12:1 differential multiplexer\nOne differential 3.3V or 2.5V LVPECL output\nTwelve selectable differential clock or data inputs\nCLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML\nMaximum output frequency: 3.2GHz\nTranslates any single ended input sig;

Low Skew,Dual,1-to-3,Differential-to-2.5V,3.3V LVPECL/ECL Fanout Buffer

The 853S013I is a low skew, high performance dual 1-to-3 Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer. The 853S013I operates with a positive or negative power supply at 2.5V or 3.3V. Guaranteed output and part-to-part skew characteristics make the 853S013I ideal for those clock distribution ·Two differential LVPECL/ECL bank outputs\n·Two differential LVPECL clock input pairs\n·PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL\n·Output frequency: 2GHz (maximum)\n·Translates any single-ended input signal to LVPECL levels with resistor bias on;

丝印代码：53S01AIL；2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

丝印代码：53S01AIL；2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

丝印代码：3S1A；2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

丝印代码：3S1A；2:1 Differential-to-LVPECL Multiplexer

Features • One LVPECL output pair • Two selectable differential LVPECL clock inputs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML • Translates LVCMOS/LVTTL input signals to LVPECL levels by using a resistor bias network on nPCLKx, nPCLKx • Part-

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

文件：601.31 Kbytes Page：20 Pages

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

文件：601.31 Kbytes Page：20 Pages

丝印代码：1BIL；LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

丝印代码：1BIL；LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

文件：601.31 Kbytes Page：20 Pages

封装/外壳：8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 包装：卷带（TR） 描述：IC CLK BUFFER 1:2 2.5GHZ 8TSSOP 集成电路（IC） 时钟缓冲器，驱动器

LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

丝印代码：3S011BIL；LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

文件：601.31 Kbytes Page：20 Pages

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ECL Fanout Buffer

文件：830.7 Kbytes Page：20 Pages

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER 1:2 2.5GHZ 8SOIC 集成电路（IC） 时钟缓冲器，驱动器

Low Skew, 1-to-2, Differential-to-2.5V, 3.3V LVPECL/ ECL Fanout Buffer

文件：601.31 Kbytes Page：20 Pages

丝印代码：3S011BIL；LVPECL/ ECL Fanout Buffer

文件：315.73 Kbytes Page：20 Pages

丝印代码：ICS3S012AIL；12:1, Different ial-to-3.3V, 2.5V LVPECL Clock/Data Mult iplexer

文件：495.39 Kbytes Page：20 Pages

丝印代码：ICS3S012AIL；12:1, Different ial-to-3.3V, 2.5V LVPECL Clock/Data Mult iplexer

文件：495.39 Kbytes Page：20 Pages

丝印代码：53S01AIL；2:1 Differential-to-LVPECL Multiplexer

文件：435.13 Kbytes Page：23 Pages

丝印代码：53S01AIL；2:1 Differential-to-LVPECL Multiplexer

文件：435.13 Kbytes Page：23 Pages

丝印代码：3S1A；2:1 Differential-to-LVPECL Multiplexer

文件：435.13 Kbytes Page：23 Pages

丝印代码：3S1A；2:1 Differential-to-LVPECL Multiplexer

文件：435.13 Kbytes Page：23 Pages

One LVPECL output pair

文件：484.39 Kbytes Page：23 Pages