Features

• One LVPECL output pair

• Two selectable differential LVPECL clock inputs

• PCLKx, nPCLKx pairs can accept the following

differential input levels: LVPECL, LVDS, CML

• Translates LVCMOS/LVTTL input signals to LVPECL levels by

using a resistor bias network on nPCLKx, nPCLKx

• Part-to-part skew: 150ps (maximum)

• Propagation delay: 490ps (maximum)

• Full 3.3V or 2.5V operating supply

• -40°C to 85°C ambient operating temperature

• Available in lead-free (RoHS 6) packages