12 Bit, 2-to-1, 3.3V, 2.5V LVPECL Clock Buffer

Features • Twelve, 2-to-1 multiplexers with LVPECL outputs • Selectable differential CLKx, nCLKx input pairs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Individual select control for each multiplex

LVPECL Clock Buffer

文件：358.36 Kbytes Page：20 Pages

12 Bit, 2-to-1, 3.3V, 2.5V LVPECL Clock Buffer

Features • Twelve, 2-to-1 multiplexers with LVPECL outputs • Selectable differential CLKx, nCLKx input pairs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Individual select control for each multiplex

12 Bit, 2-to-1, 3.3V, 2.5V LVPECL Clock Buffer

Features • Twelve, 2-to-1 multiplexers with LVPECL outputs • Selectable differential CLKx, nCLKx input pairs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 700MHz • Individual select control for each multiplex

LVPECL Clock Buffer

文件：358.36 Kbytes Page：20 Pages