Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The LVQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is no

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

文件：78.81 Kbytes Page：6 Pages

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SOP 集成电路（IC） 触发器

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The 74LVQ74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. ■ HIGH SPEED: fMAX = 250 MHz (TYP.) at VCC =

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

General Description The LVQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is no

Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

文件：78.81 Kbytes Page：6 Pages

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

文件：438.19 Kbytes Page：13 Pages

封装/外壳：14-SOIC（0.209"，5.30mm 宽） 功能：设置（预设）和复位 包装：管件 描述：IC FF D-TYPE DUAL 1BIT 14SOP 集成电路（IC） 触发器

DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR

DESCRIPTION The 74LVQ74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. ■ HIGH SPEED: fMAX = 250 MHz (TYP.) at VCC =