Triple 3-input NOR gate

DESCRIPTION The 74LVC27 is a high-performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC27 provides the 3-input NOR function. FEATURES • Wide supply voltage: 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • In

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

Octal D-type flip-flop with reset; positive-edge trigger

The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transfer • Wide supply voltage range from 1.2 to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Output drive capability 50 Ω transmission lines at +85 °C\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V;

Octal D-type flip-flop with reset; positive-edge trigger

The 74LVC273-Q100 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is tra • Automotive product qualification in accordance with AEC-Q100 (Grade 1)• Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n• Wide supply voltage range from 1.2 V to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Output dr;

Octal D-type flip-flop with reset; positive-edge trigger

The 74LVC273 has eight edge-triggered, D-type flip-flops with individual Dn inputs and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each Dn input, one set-up time before the LOW-to-HIGH clock transition, is transfer • Wide supply voltage range from 1.2 to 3.6 V\n• Inputs accept voltages up to 5.5 V\n• CMOS low power consumption\n• Direct interface with TTL levels\n• Output drive capability 50 Ω transmission lines at +85 °C\n• Complies with JEDEC standard:• JESD8-7A (1.65 V to 1.95 V)\n• JESD8-5A (2.3 V to 2.7 V;

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Triple 3-input NOR gate

DESCRIPTION The 74LVC27 is a high-performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC27 provides the 3-input NOR function. FEATURES • Wide supply voltage: 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • In

Triple 3-input NOR gate

DESCRIPTION The 74LVC27 is a high-performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC27 provides the 3-input NOR function. FEATURES • Wide supply voltage: 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • In

Triple 3-input NOR gate

DESCRIPTION The 74LVC27 is a high-performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC27 provides the 3-input NOR function. FEATURES • Wide supply voltage: 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • In

Triple 3-input NOR gate

DESCRIPTION The 74LVC27 is a high-performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The 74LVC27 provides the 3-input NOR function. FEATURES • Wide supply voltage: 1.2 to 3.6 V • In accordance with JEDEC standard no. 8-1A. • In

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：465.91 Kbytes Page：10 Pages

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：465.91 Kbytes Page：10 Pages

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：465.91 Kbytes Page：10 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20TSSOP 集成电路（IC） 触发器

封装/外壳：20-VFQFN 裸露焊盘 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20DHVQFN 集成电路（IC） 触发器

Octal D-type flip-flop with reset; positive-edge trigger

文件：715.31 Kbytes Page：16 Pages

Octal D-type flip-flop with reset; positive-edge trigger

文件：715.31 Kbytes Page：16 Pages

Octal D-type flip-flop with reset; positive-edge trigger

文件：715.31 Kbytes Page：16 Pages

Octal D-type flip-flop with reset; positive-edge trigger

文件：715.31 Kbytes Page：16 Pages