Standard-logic

The 74LVC273A provides eight positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.\n\n\tThe device is designed for operation with a power supply range of 1.65V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the •Supply Voltage Range from 1.65V to 3.6V \n•Sinks or Sources 24mA at VCC = 3V \n•CMOS Low Power Consumption \n•IOFF Supports Partial Power Down Operation \n•Inputs or Outputs accept up to 5.5V \n•Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications \n•Schmitt Trigger Action at ;

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：465.91 Kbytes Page：10 Pages

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：465.91 Kbytes Page：10 Pages

封装/外壳：20-VFQFN 裸露焊盘 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20QFN 集成电路（IC） 触发器

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：465.91 Kbytes Page：10 Pages

封装/外壳：20-TSSOP（0.173"，4.40mm 宽） 功能：复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 8BIT 20TSSOP 集成电路（IC） 触发器

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a