Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

封装/外壳：20-VFQFN 裸露焊盘 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 8BIT 20DHVQFN 集成电路（IC） 触发器

Octal D-type flip-flop with reset; positive-edge trigger

文件：715.31 Kbytes Page：16 Pages

封装/外壳：20-VFQFN 裸露焊盘 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 8BIT 20DHVQFN 集成电路（IC） 触发器

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

文件：465.91 Kbytes Page：10 Pages