Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器

封装/外壳：20-SSOP（0.209"，5.30mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 8BIT 20SSOP 集成电路（IC） 触发器

Octal D-type flip-flop with reset; positive-edge trigger

1. General description The 74LVC273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (C

Octal D-type flip-flop with reset; positive-edge trigger

DESCRIPTION The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered , D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) a

OCTAL D-TYPE FLIP-FLOP WITH CLEAR

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