BCD up/down counter

GENERAL DESCRIPTION The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: MSI

BCD up/down counter

GENERAL DESCRIPTION The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: MSI

BCD up/down counter

GENERAL DESCRIPTION The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: MSI

BCD up/down counter

GENERAL DESCRIPTION The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: MSI

BCD up/down counter

GENERAL DESCRIPTION The 74HC/HCT4510 are high-speed Si-gate CMOS devices and are pin compatible with the “4510” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: MSI

BCD to 7-segment latch/decoder/driver

GENERAL DESCRIPTION The 74HC/HCT4511 are high-speed Si-gate CMOS devices and are pin compatible with “4511” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Latch storage of BCD inputs • Blanking input • Lamp test input • Driving common cathode L

BCD to 7-segment latch/decoder/driver

1. General description The 74HC4511; 74HCT4511 is a BCD to 7-segment latch/decoder/driver with four address inputs (A, B, C, D), a latch enable input (LE), a ripple blanking input (BI), a lamp test input (LT), and seven segment outputs (a to g). When LE is LOW, the state of the segment outputs

BCD to 7-segment latch/decoder/driver

1. General description The 74HC4511; 74HCT4511 is a BCD to 7-segment latch/decoder/driver with four address inputs (A, B, C, D), a latch enable input (LE), a ripple blanking input (BI), a lamp test input (LT), and seven segment outputs (a to g). When LE is LOW, the state of the segment outputs

BCD to 7-segment latch/decoder/driver

GENERAL DESCRIPTION The 74HC/HCT4511 are high-speed Si-gate CMOS devices and are pin compatible with “4511” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Latch storage of BCD inputs • Blanking input • Lamp test input • Driving common cathode L

BCD to 7-segment latch/decoder/driver

GENERAL DESCRIPTION The 74HC/HCT4511 are high-speed Si-gate CMOS devices and are pin compatible with “4511” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Latch storage of BCD inputs • Blanking input • Lamp test input • Driving common cathode L

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

4-to-16 line decoder/demultiplexer with input latches

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is de

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514; 74HCT4514 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data o

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514-Q100 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data on An.

4-to-16 line decoder/demultiplexer with input latches

1. General description The 74HC4514-Q100 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), an enable input (E) and 16 outputs (Q0 to Q15). When LE is HIGH, the selected output is determined by the data on An.

4-to-16 line decoder/demultiplexer with input latches; inverting

1 General description The 74HC4515 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), an enable input (E) and 16 inverting outputs (Q0, to Q15). When LE is HIGH, the selected output is determined by the data on

4-to-16 line decoder/demultiplexer with input latches; inverting

FEATURES · Inverting outputs · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4515

4-to-16 line decoder/demultiplexer with input latches; inverting

GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inverting outputs • Output capability: standard • ICC category: MSI

4-to-16 line decoder/demultiplexer with input latches; inverting

GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inverting outputs • Output capability: standard • ICC category: MSI

4-to-16 line decoder/demultiplexer with input latches; inverting

1 General description The 74HC4515 is a 4-to-16 line decoder/demultiplexer having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), an enable input (E) and 16 inverting outputs (Q0, to Q15). When LE is HIGH, the selected output is determined by the data on

4-to-16 line decoder/demultiplexer with input latches; inverting

GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inverting outputs • Output capability: standard • ICC category: MSI

4-to-16 line decoder/demultiplexer with input latches; inverting

GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inverting outputs • Output capability: standard • ICC category: MSI

4-to-16 line decoder/demultiplexer with input latches; inverting

GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Inverting outputs • Output capability: standard • ICC category: MSI

Binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT4516 are high-speed Si-gate CMOS devices and are pin compatible with the “4516” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4516 are edge-triggered synchronous up/down 4-bit binary counters with a clock input

Binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT4516 are high-speed Si-gate CMOS devices and are pin compatible with the “4516” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4516 are edge-triggered synchronous up/down 4-bit binary counters with a clock input

Binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT4516 are high-speed Si-gate CMOS devices and are pin compatible with the “4516” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4516 are edge-triggered synchronous up/down 4-bit binary counters with a clock input

Binary up/down counter

GENERAL DESCRIPTION The 74HC/HCT4516 are high-speed Si-gate CMOS devices and are pin compatible with the “4516” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4516 are edge-triggered synchronous up/down 4-bit binary counters with a clock input

Dual synchronous BCD counter

GENERAL DESCRIPTION The 74HC/HCT4518 are high-speed Si-gate CMOS devices and are pin compatible with the “4518” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: MSI APPLICATIONS • Multis

Dual 4-bit synchronous binary counter

GENERAL DESCRIPTION The 74HC/HCT4520 are high-speed Si-gate CMOS devices and are pin compatible with the “4520” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4520 are dual 4-bit internally synchronous binary counters with an active HIGH clock inp

Dual 4-bit synchronous binary counter

1. General description The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH tran

Dual 4-bit synchronous binary counter

Dual 4-bit synchronous binary counter

Dual 4-bit synchronous binary counter

1. General description The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH tran

Dual 4-bit synchronous binary counter

GENERAL DESCRIPTION The 74HC/HCT4520 are high-speed Si-gate CMOS devices and are pin compatible with the “4520” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4520 are dual 4-bit internally synchronous binary counters with an active HIGH clock inp

Dual 4-bit synchronous binary counter

1. General description The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either t

Dual 4-bit synchronous binary counter

Dual 4-bit synchronous binary counter

1. General description The 74HC4520; 74HCT4520 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3) and an asynchronous master reset input (nMR). The counter advances on the LOW-to-HIGH tran

Dual 4-bit synchronous binary counter

GENERAL DESCRIPTION The 74HC/HCT4520 are high-speed Si-gate CMOS devices and are pin compatible with the “4520” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4520 are dual 4-bit internally synchronous binary counters with an active HIGH clock inp

Dual 4-bit synchronous binary counter

1. General description The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either t

Dual 4-bit synchronous binary counter

1. General description The 74HC4520-Q100; 74HCT4520-Q100 are dual 4-bit internally synchronous binary counters with two clock inputs (nCP0 and nCP1). They have buffered outputs from all 4 bit positions (nQ0 to nQ3), and an asynchronous master reset input (nMR). The counter advances on either t

DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATOR

DESCRIPTION The M54/74HC4538 is a high speed CMOS DUAL MONOSTABLEMULTIVIBRATOR fabricated insilicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. Each multivibrator features both a negative, A, and a positive, B, edge trigger

Dual retriggerable precision monostable multivibrator

1. General description The 74HC4538 is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has two trigger/retrigger inputs (nA and nB), a direct reset input (nCD), two complementary outputs (nQ and nQ), and two pins (nREXT/CEXT and nCEXT) for connecting the external ti

Dual retriggerable precision monostable multivibrator

GENERAL DESCRIPTION The 74HC/HCT4538 are high-speed Si-gate CMOS devices and are pin compatible with “4538” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Separate reset inputs • Triggering from leading or trailing edge • Output capa

Dual Retriggerable Monostable Multivibrator

General Description The MM74HC4538 high speed monostable multivibrator (one shots) is implemented in advanced silicon-gate CMOS technology. They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits.

Dual Precision Monostable Multivibrator(Retriggerable, Resettable)

The MC74HC4538A is identical in pinout to the MC14538B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This dual monostable multivibrator may be triggered by either the positive or the negative edge of an input pulse,

Dual Precision Retriggerable/Resettable Monostable Multivibrators

Description Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one short. The HD74HC4538 is retriggerable. That is, it may be triggered repe

Dual retriggerable precision monostable multivibrator

GENERAL DESCRIPTION The 74HC/HCT4538 are high-speed Si-gate CMOS devices and are pin compatible with “4538” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Separate reset inputs • Triggering from leading or trailing edge • Output capa

Dual retriggerable precision monostable multivibrator

1. General description The 74HC4538 is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has two trigger/retrigger inputs (nA and nB), a direct reset input (nCD), two complementary outputs (nQ and nQ), and two pins (nREXT/CEXT and nCEXT) for connecting the external ti

CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Dual Monostable Multivibrator General The 74HC4538D is a high speed CMOS MONOSTABLE MULTIVIBRATOR fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Ther

Dual retriggerable precision monostable multivibrator

GENERAL DESCRIPTION The 74HC/HCT4538 are high-speed Si-gate CMOS devices and are pin compatible with “4538” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Separate reset inputs • Triggering from leading or trailing edge • Output capa

Dual retriggerable precision monostable multivibrator

General description The 74HC4538-Q100 is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has two trigger/retrigger inputs (nA and nB), a direct reset input (nCD), two complementary outputs (nQ and nQ), and two pins (nREXT/CEXT and nCEXT) for connecting the external ti

CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Dual Monostable Multivibrator General The 74HC4538FT is a high speed CMOS MONOSTABLE MULTIVIBRATOR fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. There

Dual retriggerable precision monostable multivibrator

GENERAL DESCRIPTION The 74HC/HCT4538 are high-speed Si-gate CMOS devices and are pin compatible with “4538” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Separate reset inputs • Triggering from leading or trailing edge • Output capa

Dual retriggerable precision monostable multivibrator

GENERAL DESCRIPTION The 74HC/HCT4538 are high-speed Si-gate CMOS devices and are pin compatible with “4538” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. FEATURES • Separate reset inputs • Triggering from leading or trailing edge • Output capa

Dual retriggerable precision monostable multivibrator

1. General description The 74HC4538 is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has two trigger/retrigger inputs (nA and nB), a direct reset input (nCD), two complementary outputs (nQ and nQ), and two pins (nREXT/CEXT and nCEXT) for connecting the external ti

Dual retriggerable precision monostable multivibrator

General description The 74HC4538-Q100 is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has two trigger/retrigger inputs (nA and nB), a direct reset input (nCD), two complementary outputs (nQ and nQ), and two pins (nREXT/CEXT and nCEXT) for connecting the external ti

Dual retriggerable precision monostable multivibrator

General description The 74HC4538-Q100 is a dual retriggerable-resettable monostable multivibrator. Each multivibrator has two trigger/retrigger inputs (nA and nB), a direct reset input (nCD), two complementary outputs (nQ and nQ), and two pins (nREXT/CEXT and nCEXT) for connecting the external ti