74HC17价格
参考价格：￥1.2074
型号：74HC173D,652 品牌：NXP 备注：这里有74HC17多少钱，2026年最近7天走势，今日出价，今日竞价，74HC17批发/采购报价，74HC17行情走势销售排行榜，74HC17报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
丝印代码：74HC175D；CMOS Digital Integrated Circuits Silicon Monolithic Functional Description • Quad D-Type Flip-Flop with Clear General The 74HC175D is a high speed CMOS D-TYPE FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Information s | TOSHIBA 东芝 |   | ||
Quad D-type flip-flop; positive-edge trigger; 3-state GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs ( | PHILIPS 飞利浦 | | ||
Quad D-type flip-flop; positive-edge trigger; 3-state 1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co | NEXPERIA 安世 | | ||
Quad D-type flip-flop; positive-edge trigger; 3-state 1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co | NEXPERIA 安世 | | ||
Quad D-type flip-flop; positive-edge trigger; 3-state GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs ( | PHILIPS 飞利浦 | | ||
74HC173DB - Quad D-type flip-flop; positive-edge trigger; 3-state Quad D-type flip-flop; positive-edge trigger; 3-state - The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will ·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC173: CMOS level\n·For 74HCT173: TTL level; | NEXPERIA 安世 | | ||
Quad D-type flip-flop; positive-edge trigger; 3-state The 74HC173-Q100; 74HCT173-Q100 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inp | NEXPERIA 安世 | | ||
Quad D-type flip-flop; positive-edge trigger; 3-state GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs ( | PHILIPS 飞利浦 | | ||
Quad D-type flip-flop; positive-edge trigger; 3-state The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that m • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC173: CMOS level\n• For 74HCT173: TTL level\n\n• Gated input enable for hold (do nothing) mode\n• Gated output enable control mode\n• Edge-triggered D-type register\n• Asynchronous master reset\n• ESD protection:• HBM JESD22-A114F exceed; | NEXPERIA 安世 | | ||
Quad D-type flip-flop; positive-edge trigger; 3-state 1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co | NEXPERIA 安世 | | ||
Hex D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap | PHILIPS 飞利浦 | | ||
Hex D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requ | NEXPERIA 安世 | | ||
Hex D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requ | NEXPERIA 安世 | | ||
Hex D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap | PHILIPS 飞利浦 | | ||
Hex D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap | PHILIPS 飞利浦 | | ||
Hex D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold | NEXPERIA 安世 | | ||
Hex D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap | PHILIPS 飞利浦 | | ||
Hex D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap | PHILIPS 飞利浦 | | ||
Hex D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requ | NEXPERIA 安世 | | ||
Hex D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold | NEXPERIA 安世 | | ||
Hex D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold | NEXPERIA 安世 | | ||
High Speed CMOS Logic Description The 74HC175 is fabricated using a 2.5μm 5V CMOS process and consists of four D-Type flip–flops each with separate D input and common Reset and Clock inputs. The logic level present at the “D” input is transferred to the Q output during the positive-going transition of the clock p | SS | | ||
High Speed CMOS Logic Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1μA High Noise Immunity Characteristics of CMOS Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacement for obsolete components in long term programs. | SS | | ||
Quad D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q o | PHILIPS 飞利浦 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set | NEXPERIA 安世 | | ||
Quad D-Type Flip-Flop With Clear Features n Typical propagation delay: 15 ns n Wide operating supply voltage range: 2–6V n Low input current: 1 mA maximum n Low quiescent supply current: 80 mA maximum (74HC) n High output drive current: 4 mA minimum (74HC) General Description The MM74HC175 high speed D-type flip-flop wit | SOLIDSTATE | | ||
High Speed CMOS Logic Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1μA High Noise Immunity Characteristics of CMOS Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacement for obsolete components in long term programs. | SS | | ||
Quad D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q o | PHILIPS 飞利浦 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set | NEXPERIA 安世 | | ||
Quad D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q o | PHILIPS 飞利浦 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set- | NEXPERIA 安世 | | ||
Quad D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q o | PHILIPS 飞利浦 | | ||
Quad D-type flip-flop with reset; positive-edge trigger GENERAL DESCRIPTION The 74HC/HCT175 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT175 have four edge-triggered, D-type flip-flops with individual D inputs and both Q and Q o | PHILIPS 飞利浦 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC175; 74HCT175 is a quad positive-edge triggered D-type flip-flop with individual data inputs (Dn) and complementary outputs (Qn and Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set | NEXPERIA 安世 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set- | NEXPERIA 安世 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 1. General description The 74HC175-Q100; 74HCT175-Q100 are quad positive edge-triggered D-type flip-flops with individual data inputs (Dn) and both Qn and Qn outputs. The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set- | NEXPERIA 安世 | | ||
封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 4BIT 16SO 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 4BIT 16SSOP 集成电路（IC） 触发器 | ETC 知名厂家 | ETC | | |
Hex D-type flip-flop with reset; positive-edge trigger 文件：730.95 Kbytes Page：16 Pages | NEXPERIA 安世 | | ||
Hex D-type flip-flop with reset; positive-edge trigger 文件：730.95 Kbytes Page：16 Pages | NEXPERIA 安世 | | ||
Hex D-type flip-flop with reset; positive-edge trigger 文件：730.95 Kbytes Page：16 Pages | NEXPERIA 安世 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 文件：747.31 Kbytes Page：18 Pages | NEXPERIA 安世 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 文件：747.31 Kbytes Page：18 Pages | NEXPERIA 安世 | | ||
Quad D-type flip-flop with reset; positive-edge trigger 文件：747.31 Kbytes Page：18 Pages | NEXPERIA 安世 | |
74HC17产品属性
- 类型
描述
- VCC (V)：
2.0 - 6.0
- Logic switching levels：
CMOS
- Output drive capability (mA)：
± 7.8
- tpd (ns)：
17
- fmax (MHz)：
88
- Power dissipation considerations：
low
- Tamb (°C)：
-40~125
- Rth(j-a) (K/W)：
72
- Ψth(j-top) (K/W)：
1.0
- Rth(j-c) (K/W)：
30
- Package name：
SO16
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
PHI |
24+ |
SOP |
1500 |
AI芯片,车规MCU原装现货/为新能源汽车电子行业采购保驾护航 |
|||
74H00N |
25+ |
3 |
3 |
||||
恩XP |
21+ |
SOP16 |
22800 |
只做原装,质量保证 |
|||
TOS |
25+ |
SOP |
4500 |
全新原装、诚信经营、公司现货销售 |
|||
TI/德州仪器 |
2025+ |
SOIC-16 |
5000 |
原装进口价格优 请找坤融电子! |
|||
National Semiconductor |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
S |
QQ咨询 |
CDIP |
825 |
全新原装 研究所指定供货商 |
|||
National Semiconductor |
26+ |
14-PDIP |
6629 |
全新原装正品 |
|||
7631+ |
DIP-14 |
22 |
原装现货海量库存欢迎咨询 |
||||
TI(德州仪器) |
26+ |
CDIP-14 |
3600 |
十二年VIP会员,诚信经营,原装库存·可零售! |
74HC17芯片相关品牌
74HC17规格书下载地址
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- 74HC14D
- 74HC14A
- 74HC148
- 74HC147
- 74HC14
- 74HC139
74HC17数据表相关新闻
74HC164
74HC164
2023-5-2974HC193DR原装现货
74HC193DR原装正品
2021-8-774HC165PW原装现货
74HC165PW原装正品
2021-8-774HC175D,652 NXP (恩智浦) 触发器
74HC175D,652 NXP (恩智浦) 触发器
2020-7-1874HC193DR，74HC193M，74HC193N，74HC193WMX，74HC1G00DFT1
74HC193DR，74HC193M，74HC193N，74HC193WMX，74HC1G00DFT1
2020-2-1774HC14首选八零友创科技原装现货现货热卖
74HC14D的工作温度范围是-40°C ~ +125°C，针脚数是14，封装类型是SOIC。
2019-8-7
DdatasheetPDF页码索引
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