Quad 2-Input Exclusive-OR Gate

General Description This device contains four independent gates each of which performs the logic exclusive-OR function.

7/8 Diameter 5-Turn Wirewound Precision Potentiometer

SPECIAL FEATURES Center Tap Linearity Tape Rear Shaft Extension Flatted Shaft Slotted Shaft (Standard on single gang 7486 without RS) Shaft Lock (7481, 7486 only) High Torque 2–6 oz.-in. (7486 only) Additional Gangs Gold plated solder lug terminals (See optional

7/8 Diameter 5-Turn Wirewound Precision Potentiometer

SPECIAL FEATURES Center Tap Linearity Tape Rear Shaft Extension Flatted Shaft Slotted Shaft (Standard on single gang 7486 without RS) Shaft Lock (7481, 7486 only) High Torque 2–6 oz.-in. (7486 only) Additional Gangs Gold plated solder lug terminals (See optional

包装：散装 描述：SCOTCH-BRITE ROLOC SURFACE CONDI 工具 磨料和表面修整产品

Abrasives, Scotch-Brite Handpads

文件：28.61 Kbytes Page：1 Pages

Quad 2-Input Exclusive-OR Gate

D-Sub 连接器端子：插座，磷青铜，信号，22 号

D-Sub 插座扣入式连接器端子由磷青铜材料制成，采用 22 号端子端接到电线和电缆。线径范围为 28-22 AWG，用于信号电路应用。

D-Sub 插座组件：垂直，外壳尺寸 3，2.77mm

外壳尺寸为 3 的 PCB D-Sub AMPLIMITE 插座组件，中心线间距为 2.77mm，采用垂直 PCB 安装方向。用于信号电路应用，工作温度范围为 -55-105℃。

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O

FEATURES: • 1:1 and 1:2 registered buffer • 1.8V Operation • SSTL_18 style clock and data inputs • Differential CLK input • Control inputs compatible with LVCMOS levels • Flow-through architecture for optimum PCB design • Latch-up performance exceeds 100mA • ESD >2000V per MIL-STD-883, Met

Eaton safety grip locking flanged inlet, #16-12 AWG, 15A, Industrial, 125/250V, Back wiring, Black, Midget, ML3, Three-pole, Three-wire, Nylon

Special features Midget locking

7/8 Diameter 5-Turn Wirewound Precision Potentiometer

SPECIAL FEATURES Center Tap Linearity Tape Rear Shaft Extension Flatted Shaft Slotted Shaft (Standard on single gang 7486 without RS) Shaft Lock (7481, 7486 only) High Torque 2–6 oz.-in. (7486 only) Additional Gangs Gold plated solder lug terminals (See optional

Free Running Safety Clamping Lever, free-running when not engaged

文件：228.74 Kbytes Page：1 Pages

Wiha Quality Tools Toll Free: (800) 494-6104

文件：470.28 Kbytes Page：2 Pages

Wiha Quality Tools Toll Free: (800) 494-6104

文件：470.28 Kbytes Page：2 Pages

包装：散装 描述：SQUARE POWER BIT #2 X 50MM 2PK 工具 螺丝和螺母起子 - 刀头、刀片和手柄

Wiha Quality Tools Toll Free: (800) 494-6104

文件：470.28 Kbytes Page：2 Pages

Quad 2-Input Exclusive-OR Gate

General Description This device contains four independent gates each of which performs the logic exclusive-OR function.

Quad 2-Input Exclusive-OR Gates

文件：99.73 Kbytes Page：6 Pages

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

文件：647.7 Kbytes Page：15 Pages

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

文件：647.7 Kbytes Page：15 Pages

Quad 2-Input Exclusive-OR Gates

Quad 2-Input Exclusive-OR Gate

TTL HD74/HD74S Series

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES