CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16

• 25ns parallel port access time, 35ns cycle time • 50MHz serial shift frequency • Wide x16 organization offering easy expansion • Low power consumption (50mA typical) • Least/Most Significant Bit first read selected by asserting the FL/DIR pin • Four memory status flags: Empty, Full, Half-F

封装/外壳：28-DIP（0.300"，7.62mm） 功能：异步 包装：卷带（TR） 描述：IC FIFO 1KX16 PAR-SER 28DIP 集成电路（IC） FIFO 存储器

CMOS PARALLEL-TO-SERIAL FIFO

文件：246.7 Kbytes Page：11 Pages

CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16

• 25ns parallel port access time, 35ns cycle time • 50MHz serial shift frequency • Wide x16 organization offering easy expansion • Low power consumption (50mA typical) • Least/Most Significant Bit first read selected by asserting the FL/DIR pin • Four memory status flags: Empty, Full, Half-F

CMOS PARALLEL-TO-SERIAL FIFO

文件：246.7 Kbytes Page：11 Pages

CMOS PARALLEL-TO-SERIAL FIFO 1,024 x 16

• 25ns parallel port access time, 35ns cycle time • 50MHz serial shift frequency • Wide x16 organization offering easy expansion • Low power consumption (50mA typical) • Least/Most Significant Bit first read selected by asserting the FL/DIR pin • Four memory status flags: Empty, Full, Half-F

CMOS PARALLEL-TO-SERIAL FIFO

文件：246.7 Kbytes Page：11 Pages

CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16

DESCRIPTION: The IDT72105/72115/72125s are very high-speed, lowpower,dedicated, parallel-to-serial FIFOs. These FIFOs possess a 16-bit parallel input port and a serial output port with 256, 512 and 1K word depths, respectively. The ability to buffer wide word widths (x16) make these FIFOs ideal