3.3V 128K x 36 Synchronous PipeLined Burst SRAM with 2.5V I/O

The 71V25761 3.3V CMOS Synchronous SRAM is organized as 128K x 36and contains write, data, address and control registers. The burst mode feature offers the highest level of performance to the system designer, as the 71V25761 can provide four cycles of data for a single address presented to the SRAM. High system speed 200MHz (3.1ns clock access time) \nLBO input selects interleaved or linear burst mode\nSelf-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)\n3.3V core power supply\nPower down controlled by ZZ input\n2.5V I/O\nOptional - Boundary Sca;

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

128K X 36 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

Features ◆ 128K x 36 memory configuration ◆ Supports high system speed: Commercial and Industrial: – 200MHz 3.1ns clock access time – 183MHz 3.3ns clock access time – 166MHz 3.5ns clock access time ◆ LBO input selects interleaved or linear burst mode ◆ Self-timed write cycle with global wr

封装/外壳：119-BGA 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 119PBGA 集成电路（IC） 存储器

封装/外壳：119-BGA 包装：卷带（TR） 描述：IC SRAM 4.5MBIT PARALLEL 119PBGA 集成电路（IC） 存储器

128K X 36, 256K X 18 3.3V Synchronous SRAMs 2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect

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