In-System Programmable High Density PLD

Description The ispLSI 1048EA is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). Features • HIGH DENSITY PROGRAMMABLE LOGIC

In-System Programmable High Density PLD

UHF power LDMOS transistor

DESCRIPTION Silicon N-channel enhancement mode lateral D-MOS transistor encapsulated in a 2-lead flange package (SOT502A) with a ceramic cap. The common source is connected to the mounting flange. FEATURES • High power gain • Easy power control • Excellent ruggedness • Source on underside el

3.3V LVDS 4-Bit Flow-Through High Speed Differential Receiver

General Description This quad receiver is designed for high speed interconnect utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100mV, to LVTTL signal levels. LVDS provides low EMI at ultra low po

NPN SILICON PLANAR MEDIUM POWER HIGH GAIN TRANSISTOR

FEATURES * VCEO = 17.5V * 5 Amp Continuous Current * 20 Amp Pulse Current * Low Saturation Voltage * High Gain * Extremely Low Equivalent On-resistance; RCE(sat) = 50mΩ at 5A

DUAL NPN MEDIUM POWER HIGH GAIN TRANSISTORS

Summary BVCEO > 17.5V IC(cont) = 5A VCE(sat) Description Advanced process capability has been used to achieve this high performance device. Combining two NPN transistors in the SM-8 package provides a compact solution for the intended applications. Features • Dual NPN device

NPN SILICON PLANAR MEDIUM POWER HIGH GAIN TRANSISTOR

FEATURES * VCEV=50V * Very Low Saturation Voltages * High Gain * 20 Amps pulse current APPLICATIONS * LCD Backlight Convertors * Emergency Lighting * DC-DC Convertors