Description

The ispLSI 1048EA is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP).

Features

• HIGH DENSITY PROGRAMMABLE LOGIC

— 8,000 PLD Gates

— 96 I/O Pins, Eight Dedicated Inputs

— 288 Registers

— High-Speed Global Interconnects

— Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

— Small Logic Block Size for Random Logic

— Functionally Compatible with ispLSI 1048C and 1048E

• NEW FEATURES

— 100 IEEE 1149.1 Boundary Scan Testable

— ispJTAG™ In-System Programmable Via IEEE 1149.1 (JTAG) Test Access Port

— User Selectable 3.3V or 5V I/O supports Mixed Voltage Systems (VCCIO Pin)

— Open Drain Output Option

• HIGH PERFORMANCE E2CMOS® TECHNOLOGY

— fmax = 170 MHz Maximum Operating Frequency

— tpd = 5.0 ns Propagation Delay

— TTL Compatible Inputs and Outputs

— Electrically Eraseable and Reprogrammable

— Non-Volatile

— 100 Tested at Time of Manufacture

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality

— Reprogram Soldered Devices for Faster Prototyping

• OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue Logic and Structured Designs

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to Minimize Switching Noise

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global Interconnectivity

• ispDesignEXPERT™ – LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING

— Superior Quality of Results

— Tightly Integrated with Leading CAE Vendor Tools

— Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™

— PC and UNIX Platforms