Shielded Bags, Standard and Zipped

文件：30.5 Kbytes Page：1 Pages

Ultra-compact EMC/RFI Filter for Motor Drives Applications

文件：205.17 Kbytes Page：4 Pages

包装：袋 描述：BAG STATIC METAL-IN 3X5\ 静电控制，防静电，ESD，无尘室产品 静电控制屏蔽包，防静电袋、物料

Low Power Hex D-Type Latch

General Description The 100350 contains six D-type latches with true and complement outputs, a pair of common Enables (Ea and Eb), and a common Master Reset (MR). A Q output follows its D input when both Ea and Eb are LOW. When either Ea or Eb (or both) are HIGH, a latch stores the last valid dat

Inductive Sensor – With Increased Temperature Range

Features ■Threaded barrel, M8 x 1 ■Stainless steel, 1.4427 SO ■Temperatures up to +100 °C ■DC 2-wire, nom. 8.2 VDC ■Output acc. to DIN EN 60947-5-6 (NAMUR) ■M12 x 1 male connector ■ATEX category II 1 G, Ex Zone 0 at temperatures up to +80 °C ■ATEX category II 2 G. Ex Zone 1 ■ATEX categor

Low Power Hex D-Type Latch

General Description The 100350 contains six D-type latches with true and complement outputs, a pair of common Enables (Ea and Eb), and a common Master Reset (MR). A Q output follows its D input when both Ea and Eb are LOW. When either Ea or Eb (or both) are HIGH, a latch stores the last valid dat

Low Power Hex D-Type Latch

General Description The 100350 contains six D-type latches with true and complement outputs, a pair of common Enables (Ea and Eb), and a common Master Reset (MR). A Q output follows its D input when both Ea and Eb are LOW. When either Ea or Eb (or both) are HIGH, a latch stores the last valid dat

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

Low Power Hex D-Type Flip-Flop

General Description The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and C

Low Power 8-Bit Buffer with Cut-Off Drivers

General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a

Low Power 8-Bit Buffer with Cut-Off Drivers

General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a

Low Power 8-Bit Buffer with Cut-Off Drivers

General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a

Low Power 8-Bit Buffer with Cut-Off Drivers

General Description The 100352 contains an 8-bit buffer, individual inputs (Dn), outputs (Qn), and a data output enable pin (OEN). A Q output follows its D input when the OEN pin is LOW. A HIGH on OEN holds the outputs in a cut-off state. The cut-off state is designed to be more negative than a

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

Inductive Sensor

Features ■Threaded barrel, M8 x 1 ■Stainless steel, 1.4427 SO ■DC 2-wire, nom. 8.2 VDC ■Output acc. to DIN EN 60947-5-6 (NAMUR) ■M8 x 1 male connector ■ATEX category II 1 G, Ex zone 0 ■ATEX category II 1 D, Ex zone 20 ■SIL2 (Low Demand Mode) acc. to IEC 61508, PL c acc. to ISO 13849-1 wit

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

Low Power 8-Bit Register

General Description The 100353 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when CP goes HIGH. When the CEN in

Low Power 8-Bit Register with Cut-Off Drivers

General Description The 100354 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when C

Low Power 8-Bit Register with Cut-Off Drivers

General Description The 100354 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when C

Low Power 8-Bit Register with Cut-Off Drivers

General Description The 100354 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when C

Low Power 8-Bit Register with Cut-Off Drivers

General Description The 100354 contains eight D-type edge triggered, master/slave flip-flops with individual inputs (Dn), true outputs (Qn), a clock input (CP), an output enable pin (OEN), and a common clock enable pin (CEN). Data enters the master when CP is LOW and transfers to the slave when C

Low Power Quad Multiplexer/Latch

General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable (En) inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routin

Low Power Quad Multiplexer/Latch

General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable (En) inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routin

Low Power Quad Multiplexer/Latch

General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable (En) inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routin

Low Power Quad Multiplexer/Latch

General Description The 100355 contains four transparent latches, each of which can accept and store data from two sources. When both Enable (En) inputs are LOW, the data that appears at an output is controlled by the Select (Sn) inputs, as shown in the Operating Mode table. In addition to routin

包装：托盘 描述：PCB TERMINAL 连接器，互连器件 线对板

螺钉式接线端子

Low Power Hex D-Type Latch

Low Power Hex D Latch

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Low Power Hex D Flip-Flop

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4 LANE R/A TH HEADER

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4 LANE R/A TH HEADER

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4 LANE R/A TH HEADER

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4 LANE R/A TH HEADER

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4 LANE R/A TH HEADER

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4 LANE R/A TH HEADER

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zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps, 30 AWG

文件：51.97 Kbytes Page：1 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps, 30 AWG

文件：51.97 Kbytes Page：1 Pages

zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps

文件：51.98 Kbytes Page：1 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps

文件：51.98 Kbytes Page：1 Pages

zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps, 30 AWG

文件：51.97 Kbytes Page：1 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps, 30 AWG

文件：51.94 Kbytes Page：1 Pages

zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps, 26 AWG

文件：51.97 Kbytes Page：1 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps, 26 AWG

文件：51.97 Kbytes Page：1 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages

zQSFP-to-4 zQSFP Passive Cable Assembly, 100 Gbps-to-(4) 25 Gbps, 26 AWG

文件：51.97 Kbytes Page：1 Pages

ZQSFP TO 4ZQSFP BREAKOUT

文件：837.67 Kbytes Page：3 Pages