General Description

The 100351 contains six D-type edge-triggered, master/slave flip-flops with true and complement outputs, a pair of common Clock inputs (CPa and CPb) and common Master Reset (MR) input. Data enters a master when both CPa and CPb are LOW and transfers to the slave when CPa and CPb (or both) go HIGH. The MR input overrides all other inputs and makes the Q outputs LOW. All inputs have 50 kΩ pull-down resistors.

Features

■ 40 power reduction of the 100151

■ 2000V ESD protection

■ Pin/function compatible with 100151

■ Voltage compensated operating range:

−4.2V to −5.7V

■ Available to industrial grade temperature range