96kHz DIR Dolby Digital / Pro Logic II / DTS decoder Sub DSP

OUTLINE YSS932 is one chip LSI consisting of three built-in blocks : SPDIF receiver (DIR), Dolby Digital (AC-3) / Pro Logic II & DTS decoder (Main DSP) and programmable sound fields processing DSP (Sub DSP). The Sub DSP is capable of realizing various sound fields, such as virtual surround

96kHz DIR Dolby Digital / Pro Logic II / DTS decoder Sub DSP

32 W 890 to 915 MHz RF POWER AMPLIFIER

The RF Line UHF Power Amplifier . . . designed specifically for the Pan European digital 20 watt, GSM mobile radio. The MHW932 is capable of wide power range control, operates from a 12.5 volt supply and requires 100 mW of RF input power. • Specified 12.5 Volt Characteristics: RF Input Pow

LOW VOLTAGE PLL CLOCK DRIVER

Low Voltage PLL Clock Driver The MPC932 is a 3.3V compatible PLL based clock driver device targetted for zero delay applications. The device provides 6 outputs for driving clock loads plus a single dedicated PLL feedback clock output. The dedicated feedback output gives the user six choices of in

1.8V, RRIO Operational Amplifiers

文件：625.77 Kbytes Page：19 Pages

1.8V, RRIO Operational Amplifiers

文件：625.77 Kbytes Page：19 Pages

1.8V, RRIO Operational Amplifiers

文件：625.77 Kbytes Page：19 Pages