4M ??4 BANKS ??16 BIT DDR2 SDRAM

GENERAL DESCRIPTION The W9725G6JB is a 256M bits DDR2 SDRAM, organized as 4,194,304 words x 4 banks x 16 bits. This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various applications. W9725G6JB is sorted into the following speed grades: -18, -25, 25I, 25A, 25K and

4M  4 BANKS  16 BIT DDR2 SDRAM

Double Data Rate architecture: two data transfers per clock cycle

封装/外壳：84-TFBGA 包装：托盘 描述：IC DRAM 256MBIT PARALLEL 84WBGA 集成电路（IC） 存储器

Double Data Rate architecture: two data transfers per clock cycle

文件：1.035859 Mbytes Page：86 Pages

双倍数据传输速率同步动态随机存取内存-2nd generation(第二代)

封装/外壳：84-TFBGA 包装：卷带（TR） 描述：IC DRAM 256MBIT PARALLEL 84WBGA 集成电路（IC） 存储器

DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask

文件：1.11353 Mbytes Page：87 Pages

DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask

文件：1.11353 Mbytes Page：87 Pages

DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask

文件：1.11353 Mbytes Page：87 Pages

DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask

文件：1.11353 Mbytes Page：87 Pages

4M X 4 BANKS X 16 BIT DDR2 SDRAM

文件：1.11353 Mbytes Page：87 Pages

DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask

文件：1.11353 Mbytes Page：87 Pages

DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask

文件：1.11353 Mbytes Page：87 Pages