Double Data Rate architecture: two data transfers per clock cycle

GENERAL DESCRIPTION The W631GG6KB is a 1G bits DDR3 SDRAM, organized as 8,388,608 words x 8 banks x 16 bits. This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various applications. W631GG6KB is sorted into the following speed grades: -11, -12, 12I, 12A, 12K -1

Double Data Rate architecture: two data transfers per clock cycle

GENERAL DESCRIPTION The W631GG6KB is a 1G bits DDR3 SDRAM, organized as 8,388,608 words x 8 banks x 16 bits. This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various applications. W631GG6KB is sorted into the following speed grades: -11, -12, 12I, 12A, 12K -1

Double Data Rate architecture: two data transfers per clock cycle

GENERAL DESCRIPTION The W631GG6KB is a 1G bits DDR3 SDRAM, organized as 8,388,608 words x 8 banks x 16 bits. This device achieves high speed transfer rates up to 1866 Mb/sec/pin (DDR3-1866) for various applications. W631GG6KB is sorted into the following speed grades: -11, -12, 12I, 12A, 12K -1