Hybrid IC IGBT Gate Driver

Description: VLA507-01 is a hybrid integrated circuit designed for driving IGBT modules. This device operates as an isolation amplifier for these modules and provides the required electrical isolation between the input and output with an optocoupler. Features: □ Output is ±3 Amperes Maximum □

封装/外壳：8-SIP 模块，6 引线 包装：卷带（TR） 描述：IC GATE DRVR LOW-SIDE MODULE 集成电路（IC） 栅极驱动器

VLA507-01,Gate Drivers,,,Main Application - interface for IGBT and IPM devices, de-saturation protection, fault detection

HYBRID IC DRIVER FOR IGBT MODULES

HYBRID IC DRIVER FOR IGBT MODULES

IGBT Driver

PECL CLOCK SYNTHESIZER

Features • Packaged in 16 pin SOIC • Available in Pb (lead) free package • Input crystal frequency of 5 - 27 MHz • Input clock frequency of 5 - 52 MHz • Enable usage of common low-cost crystal • Differential PECL output clock frequencies up to 200 MHz • Duty cycle of 49/51 • Operation vol

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out

PECL Clock Synthesizer

Description The ICS507-01 and ICS507-02 are inexpensive ways to generate a low jitter 155.52 MHz (or other high speed) differential PECL clock output from a low frequency crystal input. Using Phase-Locked-Loop (PLL) techniques, the devices use a standard fundamental mode crystal to produce out