155M ATM INTEGRATED SAR CONTROLLER

DESCRIPTION The µPD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µPD98405 conforms to ATM Forum and

MOS INTEGRATED CIRCUIT

FEATURES • Conforms to ATM Forum. • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.3 V, 32 bits, 33 MHz) • AAL-5 SAR sublayer, ATM layer, and TC sublayer functions • Hardware sup

MOS INTEGRATED CIRCUIT

FEATURES • Conforms to ATM Forum. • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.3 V, 32 bits, 33 MHz) • AAL-5 SAR sublayer, ATM layer, and TC sublayer functions • Hardware sup

155M ATM INTEGRATED SAR CONTROLLER

DESCRIPTION The µPD98405 (NEASCOT-S20TM) is a high-performance SAR chip that performs segmentation and reassembly of ATM cells. It has a PCI bus interface, a SONET/SDH 155-Mbps framer, and a clock recovery circuit and supports an ABR function in hardware. The µPD98405 conforms to ATM Forum and

MOS INTEGRATED CIRCUIT

FEATURES • Conforms to ATM Forum. • Host bus interface supporting PCI bus/generic bus. - PCI interface (5/3.3 V, 32/64 bits, 33 MHz): Conforms to PCI Specification 2.1 - Generic bus interface (5/3.3 V, 32 bits, 33 MHz) • AAL-5 SAR sublayer, ATM layer, and TC sublayer functions • Hardware sup