MOS INTEGRATED CIRCUIT

GRAPHICS LSI

MOS INTEGRATED CIRCUIT

GRAPHICS LSI

CMOS SUPERSYNC FIFOO 8,192 x 18, 16,384 x 18

DESCRIPTION: The IDT72255/72265 are monolithic, CMOS, high capacity, high speed, low power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, local area networks (LANs),

CMOS SUPERSYNC FIFO

DESCRIPTION: The IDT72255LA/72265LA are exceptionally deep, high speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write controls. These FIFOs offer numerous improvements over previous SuperSync FIFOs, including the following: • The limitation of the frequency of one clock inp

CMOS SuperSync FIFO™ 8,192 x 18 16,384 x 18

FEATURES • Choose among the following memory organizations: IDT72255LA — 8,192 x 18 IDT72265LA — 16,384 x 18 • Pin-compatible with the IDT72275/72285 SuperSync FIFOs • 10ns read/write cycle time (8ns access time) • Fixed, low first word data latency time • Auto power down minimizes standby

CMOS SuperSync FIFO

文件：328.5 Kbytes Page：27 Pages

CMOS SuperSync FIFO

文件：488.38 Kbytes Page：27 Pages