| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
U74LVC74A | DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 |   | |
U74LVC74A | DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR ANDPRESET | UTC 友顺 | | |
DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS 文件：220.53 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS 文件：220.53 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGETRIGGERED D-TYPE FLIP-FLOPS 文件：220.53 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 | | ||
DUAL POSITIVE-EDGE TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET 文件：203.39 Kbytes Page：7 Pages | UTC 友顺 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c | Philips 飞利浦 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger | ETC 知名厂家 | ETC | | |
Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input | NEXPERIA 安世 | | ||
Dual D-type flip-flop with set and reset; positive-edge trigger | ETC 知名厂家 | ETC | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
BOSCH/博世 |
2450+ |
QFP |
9850 |
只做原厂原装正品现货或订货假一赔十! |
|||
UTC/友顺 |
24+ |
NA/ |
21250 |
原厂直销,现货供应,账期支持! |
|||
ST |
23+ |
TO220 |
16900 |
正规渠道,只有原装! |
|||
ST |
26+ |
TO220 |
60000 |
只有原装 可配单 |
|||
UTC |
25+ |
TSSOP-14 |
20000 |
原装正品价格优惠,志同道合共谋发展 |
|||
新 |
5 |
全新原装 货期两周 |
|||||
ST |
24+ |
2 |
|||||
INTEL |
25+ |
原厂原封装 |
86720 |
全新原装进口现货价格优惠 本公司承诺原装正品假一赔 |
|||
UNI-SEMI宇力半导体 |
24+ |
DIP16 |
45000 |
宇力原厂渠道供应 |
|||
INTER |
07+ |
BGA |
51 |
普通 |
U74LVC74A规格书下载地址
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深圳科雨电子有限公司，联系人：卢小姐 手机：18975515225 原装正品 大量现货，有需要的可以联系我 QQ:97877805 微信：wei555222777
2019-8-21
DdatasheetPDF页码索引
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