Features

● DSI Receiver

 Configurable 1- up to 4-Data-Lane DSI Link with

bi-directional support on Data Lane 0

 Maximum bit rate of 1 Gbps/lane

 Video input data formats:

- RGB565 16-bits per pixel

- RGB666 18-bits per pixel

- RGB666 loosely packed 24-bits per pixel

- RGB888 24-bits per pixel

 Video frame size:

- Up to 1600×1200 24-bits per pixel resolution to

single-link LVDS display panel, limited by 135

MHz LVDS speed

- Up to WUXGA resolutions (1920×1200 24-bits

pixels) to dual-link LVDS display panel, limited by

4 Gbps DSI link speed

 Supports Video Stream packets for video data

transmission.

 Supports generic long packets for accessing the

chip's register set

 Supports the path for Host to control the on-chip

I

2C Master

● LVDS FPD Link Transmitter

 Supports single-link or dual-link

 Maximum pixel clock frequency of 135 MHz.

 Maximum pixel clock speed of 135 MHz for singlelink or 270 MHz for dual-link

 Supports display up to 1600×1200 24-bits per

pixel resolution for single-link, or up to 1920×1200

24-bits resolutions for dual-link

 Supports the following pixel formats:

- RGB666 18-bits per pixel

- RGB888 24-bits per pixel

 Features Toshiba Magic Square algorithm which

enables a RGB666 display panel to produce a

display quality almost equivalent to that of an

RGB888 24-bits panel

 Flexible mapping of parallel data input bit ordering

 Supports programmable clock polarity

 Supports two power saving states

- Sleep state, when receiving DSI ULPS signaling

- Standby state, entered by STBY pin assertion

● System Operation

 Host configures the chip through DSI link

 Through DSI link, Host accesses the chip register

set using Generic Write and Read packets. One

Generic Long Write packet can write to multiple

contiguous register addresses

 Includes an I2C Master function which is controlled

by Host through DSI link (multi-master is not

supported)

 Power management features to save power

 Configuration registers is also accessible through

I

2C Slave interface

● Clock Source

 LVDS pixel clock source is either from external

clock EXTCLK or derived from DSICLK.

 A built-in PLL generates the high-speed LVDS

serializing clock requiring no external components

● Digital Input/Output Signals

 All Digital Input signals are 3.3V tolerant

 All Digital Output signals can output 1.8V or 3.3V

depending on IO supply voltage

● Power supply

 MIPI® DSI D-PHYSM: 1.2 V

 LVDS PHY: 1.2V and 1.8 V

 I/O: 1.8 V or 3.3V (all IO supply pins

must be same level)

 Digital Core: 1.2 V

● Power Consumption

 Power Down State is achieved by:

1. Reset asserted

2. EXTCLK not toggling

3. STBY = 0

4. DSI in ULPS Drive

● AEC-Q100 qualified with the following

definition (Only TC9593XB)

 Gade3: -40 °C to 85 °C ambient operating

temprature range

● Packaging Information

 TC9593XBG BGA64 (0.65mm ball pitch)

- Supports DSI-RX 4-data-lanes + Dual-Link LVDSTX

- 6.0mm × 6.0mm × 1.0mm

 TC9592XBG BGA49 (0.65mm ball pitch)

- Supports DSI-RX 4-data-lanes + Single-Link

LVDS-TX

- 5.0mm × 5.0mm × 1.0mm