Member of the Texas Instruments

Widebus+ Family

Pinout Optimizes DDR-II DIMM PCB Layout

Configurable as 25-Bit 1:1 or 14-Bit 1:2

Registered Buffer

Chip-Select Inputs Gate the Data Outputs

from Changing State and Minimizes System

Power Consumption

Output Edge-Control Circuitry Minimizes

Switching Noise in an Unterminated Line

Supports SSTL_18 Data Inputs

Differential Clock (CLK and CLK) Inputs

Supports LVCMOS Switching Levels on the

Control and RESET Inputs

RESET Input Disables Differential Input

Receivers, Resets All Registers, and

Forces All Outputs Low

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 5000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

description/ordering information

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the

1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout

configuration, two devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the LVCMOS reset (RESET) and LVCMOS control (Cn) inputs. All outputs are

edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.

The SN74SSTU32864 operates from a differential clock (CLK and CLK). Data are registered at the crossing

of CLK going high and CLK going low.

The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to

register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low)

to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired

to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration,

the A6, D6, and H6 terminals are driven low and should not be used.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET and Cn inputs always

must be held at a valid logic high or low level.

The two VREF pins (A3 and T3), are connected together internally by approximately 150 Ω. However, it is

necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin

should be terminated with a VREF coupling capacitor.