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SN74LVTH182512DGGR中文资料

厂家型号

SN74LVTH182512DGGR

文件大小

655.55Kbytes

页面数量

39

功能描述

3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

特定功能逻辑 3.3-V ABT w/18-Bit Univ Bus Transceiver

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

TI2

SN74LVTH182512DGGR数据手册规格书PDF详情

Members of the Texas Instruments

SCOPE E Family of Testability Products

Members of the Texas Instruments

WidebusE Family

State-of-the-Art 3.3-V ABT Design Supports

Mixed-Mode Signal Operation (5-V Input

and Output Voltages With 3.3-V VCC)

Support Unregulated Battery Operation

Down to 2.7 V

UBT E (Universal Bus Transceiver)

Combines D-Type Latches and D-Type

Flip-Flops for Operation in Transparent,

Latched, or Clocked Mode

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

B-Port Outputs of ’LVTH182512 Devices

Have Equivalent 25-W Series Resistors, So

No External Resistors Are Required

Compatible With the IEEE Std 1149.1-1990

(JTAG) Test Access Port and

Boundary-Scan Architecture

SCOPE E Instruction Set

– IEEE Std 1149.1-1990 Required

Instructions and Optional CLAMP and

HIGHZ

– Parallel-Signature Analysis at Inputs

– Pseudo-Random Pattern Generation

From Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes

Package Options Include 64-Pin Plastic

Thin Shrink Small Outline (DGG) and 64-Pin

Ceramic Dual Flat (HKC) Packages Using

0.5-mm Center-to-Center Spacings

description

The ’LVTH18512 and ’LVTH182512 scan test devices with 18-bit universal bus transceivers are members of

the Texas Instruments SCOPEE testability integrated-circuit family. This family of devices supports IEEE Std

1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test

circuitry is accomplished via the 4-wire test access port (TAP) interface.

Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the

capability to provide a TTL interface to a 5-V system environment.

In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type

flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit

transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples

of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP

in the normal mode does not affect the functional operation of the SCOPEE universal bus transceivers.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when

LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high logic level.

Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B

outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar

to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.

In the test mode, the normal operation of the SCOPEE universal bus transceivers is inhibited, and the test

circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry

performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.

Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),

test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs

other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern

generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The B-port outputs of ’LVTH182512, which are designed to source or sink up to 12 mA, include equivalent 25-W

series resistors to reduce overshoot and undershoot.

The SN54LVTH18512 and SN54LVTH182512 are characterized for operation over the full military temperature

range of –55°C to 125°C. The SN74LVTH18512 and SN74LVTH182512 are characterized for operation from

–40°C to 85°C.

SN74LVTH182512DGGR产品属性

  • 类型

    描述

  • 型号

    SN74LVTH182512DGGR

  • 功能描述

    特定功能逻辑 3.3-V ABT w/18-Bit Univ Bus Transceiver

  • RoHS

  • 制造商

    Texas Instruments

  • 系列

    SN74ABTH18502A

  • 工作电源电压

    5 V

  • 封装/箱体

    LQFP-64

  • 封装

    Tube

更新时间:2025-10-9 18:51:00
供应商 型号 品牌 批号 封装 库存 备注 价格
TI/德州仪器
25+
TSSOP
32360
TI/德州仪器全新特价SN74LVTH182512DGGR即刻询购立享优惠#长期有货
TI(德州仪器)
24+
TSSOP646
2317
只做原装,提供一站式配单服务,代工代料。BOM配单
TI
23+
TSSOP64
6500
原装正品,假一罚十
TEXAS
24+
SOP
1650
TI
24+
TSSOP
6868
原装现货,可开13%税票
TexasInstruments
18+
ICSCAN-TEST-DEV/XCVR64-T
6800
公司原装现货/欢迎来电咨询!
Texas Instruments
24+
64-TSSOP
56200
一级代理/放心采购
TI
25+
SSOP-64
932
就找我吧!--邀您体验愉快问购元件!
TI(德州仪器)
2021+
TSSOP-64
499
TI/德州仪器
23+
TSSOP
50000
全新原装正品现货,支持订货

SN74LVTH182512DGGR 价格

参考价格:¥28.8877

型号:SN74LVTH182512DGGR 品牌:TI 备注:这里有SN74LVTH182512DGGR多少钱,2025年最近7天走势,今日出价,今日竞价,SN74LVTH182512DGGR批发/采购报价,SN74LVTH182512DGGR行情走势销售排排榜,SN74LVTH182512DGGR报价。