位置:SN74LVTH182512DGGR.B > SN74LVTH182512DGGR.B详情
SN74LVTH182512DGGR.B中文资料
SN74LVTH182512DGGR.B数据手册规格书PDF详情
Members of the Texas Instruments
SCOPE E Family of Testability Products
Members of the Texas Instruments
WidebusE Family
State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
Support Unregulated Battery Operation
Down to 2.7 V
UBT E (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
B-Port Outputs of ’LVTH182512 Devices
Have Equivalent 25-W Series Resistors, So
No External Resistors Are Required
Compatible With the IEEE Std 1149.1-1990
(JTAG) Test Access Port and
Boundary-Scan Architecture
SCOPE E Instruction Set
– IEEE Std 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
Package Options Include 64-Pin Plastic
Thin Shrink Small Outline (DGG) and 64-Pin
Ceramic Dual Flat (HKC) Packages Using
0.5-mm Center-to-Center Spacings
description
The ’LVTH18512 and ’LVTH182512 scan test devices with 18-bit universal bus transceivers are members of
the Texas Instruments SCOPEE testability integrated-circuit family. This family of devices supports IEEE Std
1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPEE universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB is low, the B
outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is similar
to A-to-B data flow but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPEE universal bus transceivers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The B-port outputs of ’LVTH182512, which are designed to source or sink up to 12 mA, include equivalent 25-W
series resistors to reduce overshoot and undershoot.
The SN54LVTH18512 and SN54LVTH182512 are characterized for operation over the full military temperature
range of –55°C to 125°C. The SN74LVTH18512 and SN74LVTH182512 are characterized for operation from
–40°C to 85°C.
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
TI |
16+ |
TSSOP-64 |
8000 |
原装现货请来电咨询 |
|||
TI |
24+ |
TSSOP-64 |
90000 |
一级代理商进口原装现货、假一罚十价格合理 |
|||
TI德州仪器 |
22+ |
24000 |
原装正品现货,实单可谈,量大价优 |
||||
TI/德州仪器 |
23+ |
QFP |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
TexasInstruments |
18+ |
ICSCAN-TEST-DEV/XCVR64-L |
6800 |
公司原装现货/欢迎来电咨询! |
|||
Texas Instruments |
24+ |
64-LQFP(10x10) |
56200 |
一级代理/放心采购 |
|||
TI |
25+ |
QFP-64 |
160 |
就找我吧!--邀您体验愉快问购元件! |
|||
TI/德州仪器 |
24+ |
LQFP-64 |
9600 |
原装现货,优势供应,支持实单! |
|||
TI |
23+ |
N/A |
7560 |
原厂原装 |
|||
TI/德州仪器 |
23+ |
LQFP-64 |
50000 |
全新原装正品现货,支持订货 |
SN74LVTH182512DGGR.B 资料下载更多...
SN74LVTH182512DGGR.B 芯片相关型号
- 15054
- 74LVTH182512DGGRG4.B
- 74LVTH18512DGGRG4.B
- 74LVTH18514DGGRG4.B
- AMK316BBJ227ML-TE
- ATS-06H-44-C1-R0
- CLVC573AQPWRG4Q1.B
- CLVC574AQDWRG4Q1
- CLVC574AQDWRG4Q1.B
- CLVC574AQPWRG4Q1
- CLVC574AQPWRG4Q1.B
- LNT1K103MSE
- LNT1K104MSE
- LNT1K153MSE
- LNT1K154MSE
- LNT1K223MSE
- LNT1K224MSE
- LNT1K333MSE
- SN74LVTH182512DGGR
- SN74LVTH18512DGGR
- SN74LVTH18512DGGR.B
- SN74LVTH18514DGGR
- SN74LVTH18514DGGR.B
- TLV5535IPWR.A
- TLV5604CD
- TLV5604CD.A
- TLV5604CDG4
- TLV5604CDR
- TLV5604CDR.A
- TLV5604ID.A
Datasheet数据表PDF页码索引
- P1
- P2
- P3
- P4
- P5
- P6
- P7
- P8
- P9
- P10
- P11
- P12
- P13
- P14
- P15
- P16
- P17
- P18
- P19
- P20
- P21
- P22
- P23
- P24
- P25
- P26
- P27
- P28
- P29
- P30
- P31
- P32
- P33
- P34
- P35
- P36
- P37
- P38
- P39
- P40
- P41
- P42
- P43
- P44
- P45
- P46
- P47
- P48
- P49
- P50
- P51
- P52
- P53
- P54
- P55
- P56
- P57
- P58
- P59
- P60
- P61
- P62
- P63
- P64
- P65
- P66
- P67
- P68
- P69
- P70
- P71
- P72
- P73
- P74
- P75
- P76
- P77
- P78
- P79
- P80
- P81
- P82
- P83
- P84
- P85
- P86
- P87
- P88
- P89
- P90
- P91
- P92
- P93
- P94
- P95
- P96
- P97
- P98
- P99
- P100
- P101
- P102
- P103
- P104
- P105