1 Features

• Wide operating range of 1.65V to 5.5V

• 5.5V tolerant input pins

• LVxT enhanced inputs combined with open-drain

outputs provide maximum voltage translation

flexibility:

– Over 6.67Mbps operation, (RPU = 1kΩ,

CL = 30pF)

– Up translation from 1.2V to 5V with 1.8V supply

– Down translation from 5V to 0.8V or even less

with any valid supply

• Supports standard function pinout

• Latch-up performance exceeds 250mA

per JESD 17

2 Applications

• Enable or disable a digital signal

• Controlling an indicator LED

• Translation between communication modules and

system controllers

3 Description

The SN74LV6T07-EP device contains six

independent buffers with open-drain outputs. Each

buffer performs the Boolean function Y = A in positive

logic.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2V input to 1.8V output or 1.8V input

to 3.3V output). In addition, the 5-V tolerant input pins

enable down translation (for example, 3.3V to 2.5V

output).