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SN74ALVCH162601GR中文资料

厂家型号

SN74ALVCH162601GR

文件大小

601.46Kbytes

页面数量

19

功能描述

18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

通用总线函数 Tri-State 16-Bit

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

TI2

SN74ALVCH162601GR数据手册规格书PDF详情

FEATURES

· Member of the Texas Instruments Widebus™

Family

· EPIC™ (Enhanced-Performance Implanted

CMOS) Submicron Process

· UBT™ (Universal Bus Transceiver) Combines

D-Type Latches and D-Type Flip-Flops for

Operation in Transparent, Latched, Clocked,

or Clock-Enabled Modes

· B-Port Outputs Have Equivalent 26-W Series

Resistors, So No External Resistors Are

Required

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Latch-Up Performance Exceeds 250 mA Per

JESD 17

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages

DESCRIPTION

This 18-bit universal bus transceiver is designed for

1.65-V to 3.6-V VCC operation.

The SN74ALVCH162601 combines D-type latches

and D-type flip-flops to allow data flow in transparent,

latched, clocked, and clock-enabled modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),

and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and

CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When

LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is

stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is low, the outputs are active.

When OEAB is high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.

The B-port outputs include equivalent 26-W series resistors to reduce overshoot and undershoot.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

The SN74ALVCH162601 is characterized for operation from -40°C to 85°C.

SN74ALVCH162601GR产品属性

  • 类型

    描述

  • 型号

    SN74ALVCH162601GR

  • 功能描述

    通用总线函数 Tri-State 16-Bit

  • RoHS

  • 制造商

    Texas Instruments

  • 逻辑类型

    CMOS

  • 逻辑系列

    74VMEH

  • 电路数量

    1

  • 传播延迟时间

    10.1 ns

  • 电源电压-最大

    3.45 V

  • 电源电压-最小

    3.15 V

  • 最大工作温度

    + 85 C

  • 最小工作温度

    0 C

  • 封装/箱体

    TSSOP-48

  • 封装

    Reel

更新时间:2025-10-10 15:08:00
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SN74ALVCH162601GR 价格

参考价格:¥5.8466

型号:SN74ALVCH162601GR 品牌:TI 备注:这里有SN74ALVCH162601GR多少钱,2025年最近7天走势,今日出价,今日竞价,SN74ALVCH162601GR批发/采购报价,SN74ALVCH162601GR行情走势销售排排榜,SN74ALVCH162601GR报价。