位置:SN74ACT7813-15DL > SN74ACT7813-15DL详情

SN74ACT7813-15DL中文资料

厂家型号

SN74ACT7813-15DL

文件大小

326.06Kbytes

页面数量

17

功能描述

64 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

先进先出 64 x 18 synchronous 先进先出 memory

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

TI2

SN74ACT7813-15DL数据手册规格书PDF详情

Member of the Texas Instruments

WidebusE Family

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident

Read and Write Operations Synchronized

to Independent System Clocks

Input-Ready Flag Synchronized to Write

Clock

Output-Ready Flag Synchronized to Read

Clock

64 Words by 18 Bits

Low-Power Advanced CMOS Technology

Half-Full Flag and Programmable

Almost-Full/Almost-Empty Flag

Bidirectional Configuration and Width

Expansion Without Additional Logic

Fast Access Times of 12 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

Data Rates up to 67 MHz

Pin-to-Pin Compatible With SN74ACT7803

and SN74ACT7805

Packaged in Shrink Small-Outline 300-mil

Package Using 25-mil Center-to-Center

Spacing

description

The SN74ACT7813 is a 64-word × 18-bit FIFO

suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two

devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and

GND pins, along with Texas Instruments patented output edge control (OECE) circuit, dampen simultaneous

switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input

ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low

and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless

of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four

WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes

the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be

reset upon power up.

The SN74ACT7813 is characterized for operation from 0°C to 70°C.

SN74ACT7813-15DL产品属性

  • 类型

    描述

  • 型号

    SN74ACT7813-15DL

  • 功能描述

    先进先出 64 x 18 synchronous 先进先出 memory

  • RoHS

  • 制造商

    IDT

  • 数据总线宽度

    18 bit

  • 总线定向

    Unidirectional

  • 存储容量

    4 Mbit

  • 定时类型

    Synchronous

  • 组织

    256 K x 18

  • 最大时钟频率

    100 MHz

  • 访问时间

    10 ns

  • 电源电压-最大

    3.6 V

  • 电源电压-最小

    6 V

  • 最大工作电流

    35 mA

  • 最大工作温度

    + 85 C

  • 封装/箱体

    TQFP-80

更新时间:2025-10-8 8:12:00
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只做原装,提供一站式配单服务,代工代料。BOM配单
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公司原装现货/欢迎来电咨询!
Texas Instruments
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一级代理/放心采购
TI(德州仪器)
2447
SSOP-56
315000
20个/管一级代理专营品牌!原装正品,优势现货,长期
TI
25+
SSOP-56
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就找我吧!--邀您体验愉快问购元件!
TI/德州仪器
24+
SSOP-56
9600
原装现货,优势供应,支持实单!
TI(德州仪器)
23+
SSOP-56
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原装正品,支持实单
TI/德州仪器
25+
SSOP-56
9980
只做原装 支持实单
TI
23+
原厂封装
28223
公司原装现货!主营品牌!可含税欢迎查询
TI
2023+
3000
进口原装现货