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SN74ACT7813-15DL.A中文资料

厂家型号

SN74ACT7813-15DL.A

文件大小

326.06Kbytes

页面数量

17

功能描述

64 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI2

SN74ACT7813-15DL.A数据手册规格书PDF详情

Member of the Texas Instruments

WidebusE Family

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident

Read and Write Operations Synchronized

to Independent System Clocks

Input-Ready Flag Synchronized to Write

Clock

Output-Ready Flag Synchronized to Read

Clock

64 Words by 18 Bits

Low-Power Advanced CMOS Technology

Half-Full Flag and Programmable

Almost-Full/Almost-Empty Flag

Bidirectional Configuration and Width

Expansion Without Additional Logic

Fast Access Times of 12 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

Data Rates up to 67 MHz

Pin-to-Pin Compatible With SN74ACT7803

and SN74ACT7805

Packaged in Shrink Small-Outline 300-mil

Package Using 25-mil Center-to-Center

Spacing

description

The SN74ACT7813 is a 64-word × 18-bit FIFO

suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two

devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and

GND pins, along with Texas Instruments patented output edge control (OECE) circuit, dampen simultaneous

switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input

ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low

and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless

of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four

WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes

the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be

reset upon power up.

The SN74ACT7813 is characterized for operation from 0°C to 70°C.

更新时间:2025-10-8 16:21:00
供应商 型号 品牌 批号 封装 库存 备注 价格
TI
22+
56SSOP
9000
原厂渠道,现货配单
TI
24+
5000
自己现货
TexasInstruments
18+
ICCLOCKEDFIFOMEMORY56-SS
6800
公司原装现货/欢迎来电咨询!
Texas Instruments
24+
56-SSOP
53200
一级代理/放心采购
TI
25+
SSOP-56
1001
就找我吧!--邀您体验愉快问购元件!
Texas Instruments(德州仪器)
24+
56-BSSOP (0.295, 7.50mm Width
690000
代理渠道/支持实单/只做原装
TI
2025+
SSOP-56
16000
原装优势绝对有货
Rochester
25+
电联咨询
7800
公司现货,提供拆样技术支持
TI
24+
SSOP56
5000
只做原装公司现货
TI
23+
SSOP56
8650
受权代理!全新原装现货特价热卖!