Member of the Texas Instruments

Widebus Family

Compatible With IEEE Std 1149.1-1990

JTAG) Test Access Port and

Boundary-Scan Architecture

Includes D-Type Flip-Flops and Control

Circuitry to Provide Multiplexed

Transmission of Stored and Real-Time Data

Two Boundary-Scan Cells Per I/O for

Greater Flexibility

SCOPE Instruction Set

– IEEE Std 1149.1-1990 Required

Instructions, Optional INTEST, and

P1149.1A CLAMP and HIGHZ

– Parallel Signature Analysis at Inputs

With Masking Option

– Pseudorandom Pattern Generation From

Outputs

– Sample Inputs/Toggle Outputs

– Binary Count From Outputs

– Device Identification

– Even-Parity Opcodes