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SN65LVDS116DGG中文资料
SN65LVDS116DGG数据手册规格书PDF详情
FEATURES
· One Receiver and Sixteen Line Drivers Meet
or Exceed the Requirements of ANSI
EIA/TIA-644 Standard
· Typical Data Signaling Rates to 400 Mbps or
Clock Frequencies to 400 MHz
· Enabling Logic Allows Separate Control of
Each Bank of Four Channels or 2-Bit
Selection of Any One of the Four Banks
· Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a 100-W
Load
· Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Termination Networks
· Propagation Delay Times < 4.7 ns
· Output Skew Is < 300 ps and Part-to-Part
Skew < 1.5 ns
· Total Power Dissipation Typically 470 mW
With All Ports Enabled and at 200 MHz
· Driver Outputs or Receiver Input Is High
Impedance When Disabled or With VCC < 1.5
V
· Bus-Pin ESD Protection Exceeds 12 kV
· Packaged in Thin Shrink Small-Outline
Package With 20-Mil Terminal Pitch
DESCRIPTION
The SN65LVDS116 is one differential line receiver
connected to sixteen differential line drivers that
implement the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS, as specified in
EIA/TIA-644, is a data signaling technique that offers
the low-power, low-noise coupling, and fast switching
speeds to transmit data at relatively long distances.
(Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of
the media, the noise coupling to the environment, and
other system characteristics.)
The intended application of this device and signaling
technique is for point-to-point or multidrop baseband
data transmission over controlled impedance media of approximately 100 W. The transmission media may
be printed-circuit board traces, backplanes, or cables.
The large number of drivers integrated into the same
substrate along with the low pulse skew of balanced
signaling, allows extremely precise timing alignment
of the signals repeated from the input. This is
particularly advantageous in system clock distribution.
The SN65LVDS116 is characterised for operation
from –40°C to 85°C.
SN65LVDS116DGG产品属性
- 类型
描述
- 型号
SN65LVDS116DGG
- 功能描述
时钟驱动器及分配
- 1
16 LVDS Clock Fanout Buffer
- RoHS
否
- 制造商
Micrel
- 1
4
- 输出类型
Differential
- 最大输出频率
4.2 GHz
- 电源电压-最小
5 V
- 最大工作温度
+ 85 C
- 封装/箱体
SOIC-8
- 封装
Reel
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
TI(德州仪器) |
24+ |
标准封装 |
9048 |
原厂直销,大量现货库存,交期快。价格优,支持账期 |
|||
TI/德州仪器 |
25+ |
TSSOP64 |
32360 |
TI/德州仪器全新特价SN65LVDS116DGGR即刻询购立享优惠#长期有货 |
|||
TI(德州仪器) |
24+ |
TSSOP-64-6 |
7810 |
支持大陆交货,美金交易。原装现货库存。 |
|||
24+ |
3000 |
自己现货 |
|||||
TI |
25+ |
TSSOP |
2659 |
原装正品!公司现货!欢迎来电洽谈! |
|||
TexasInstruments |
18+ |
IC1:16LVDSSPLITTER64-TSS |
6800 |
公司原装现货/欢迎来电咨询! |
|||
Texas Instruments |
24+ |
64-TSSOP |
56300 |
一级代理/放心采购 |
|||
TI |
25+ |
SSOP-64 |
932 |
就找我吧!--邀您体验愉快问购元件! |
|||
TI |
23+ |
N/A |
560 |
原厂原装 |
|||
TI/德州仪器 |
23+ |
TSSOP |
50000 |
全新原装正品现货,支持订货 |
SN65LVDS116DGGR 价格
参考价格:¥39.8656
SN65LVDS116DGG 资料下载更多...
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