1 Features

1• High Performance LVPECL and LVCMOS PLL

Clock Synchronizer

• Two Reference Clock Inputs (Primary and

Secondary Clock) for Redundancy Support With

Manual or Automatic Selection

• Accepts LVCMOS Input Frequencies Up to

200 MHz

• VCXO_IN Clock is Synchronized to One of the

Two Reference Clocks

• VCXO_IN Frequencies Up to 2 GHz (LVPECL)

• Outputs can be a Combination of LVPECL and

LVCMOS (Up to Five Differential LVPECL Outputs

or Up to 10 LVCMOS Outputs)

• Output Frequency is Selectable by x1, /2, /3, /4,

/6, /8, /16 on Each Output Individually

• Efficient Jitter Cleaning from Low PLL Loop

Bandwidth

• Low Phase Noise PLL Core

• Programmable Phase Offset (PRI_REF and

SEC_REF to Outputs)

• Wide Charge Pump Current Range From

200 μA to 3 mA

• Analog and Digital PLL Lock Indication

• Provides VBB Bias Voltage Output for Single-

Ended Input Signals (VCXO_IN)

• Frequency Hold Over Mode Improves Fail-Safe

Operation

• Power-Up Control Forces LVPECL Outputs to Tri-

State at VCC < 1.5 V

• SPI Controllable Device Setting

• 3.3-V Power Supply

• High-Performance 52 Pin Ceramic Quad Flat

Pack (HFG)

• Rad-Tolerant : 50 kRad (Si) TID

• QML-V Qualified, SMD 5962-07230

• Military Temperature Range: –55°C to 125°C Tcase

• Engineering Evaluation (/EM) Samples are

Available

(1) These units are intended for engineering evaluation only.

They are processed to a non-compliant flow (for example, no

burn-in, and so forth) and are tested to temperature rating of

25°C only. These units are not suitable for qualification,

production, radiation testing or flight use. Parts are not

warranted for performance on full MIL specified temperature

range of –55°C to 125°C or operating life.

2 Applications

• Low-Jitter Clock Distribution

• SERDES Links

• Analog Data Converters

• Digital-to-Analog Converters

3 Description

The CDCM7005-SP is a high-performance, low

phase noise and low skew clock synchronizer that

synchronizes a VCXO (voltage controlled crystal

oscillator) or VCO (voltage controlled oscillator)

frequency to one of the two reference clocks. The

programmable pre-divider M and the feedbackdividers

N and P give a high flexibility to the

frequency ratio of the reference clock to VC(X)O as

VC(X)O_IN / PRI_REF = (N × P) / M or VC(X)O_IN /

SEC_REF = (N × P) / M.

VC(X)O_IN clock operates up to 2 GHz. Through the

selection of external VC(X)O and loop filter

components, the PLL loop bandwidth and damping

factor can be adjust to meet different system

requirements.