1 Features

• Clock frequency range: DC to 24 MHz

• 1.2-V to 1.8-V LVCMOS clock level translation:

– VDD_IN = 1.2 V ± 10%

– VDD_OUT = 1.8 V ± 10%

• Low additive jitter and phase noise:

– 0.8-ps maximum 12-kHz to 5-MHz additive

RMS jitter (fout = 24 MHz)

– –120-dBc/Hz maximum phase noise at 1-kHz

offset (fout = 24 MHz)

– –148-dBc/Hz maximum phase noise floor (fout =

24 MHz, foffset ≥ 1 MHz)

• 5-ns 20% to 80% rise/fall time

• 10-ns propagation delay

• Low current consumption

• –40°C to 85°C operating temperature range

2 Applications

• FPGA/processor clock buffering/level translation in

personal electronics

• 1.2-V clock buffer and level translator in servers

and add-in cards

3 Description

The CDCBT1001 is a 1.2-V to 1.8-V clock buffer

and level translator. The VDD_IN pin supply voltage

defines the input LVCMOS clock level. The VDD_OUT

pin supply voltage defines the output LVCMOS clock

level. VDD_IN = 1.2 V ± 10%. VDD_OUT = 1.8 V ±

10%

The 12-kHz to 5-MHz additive RMS jitter at 24 MHz is

less than 0.8 ps.