1 Features

• Quad channel

• 14-Bit resolution

• Maximum clock rate: 500 MSPS

• Input bandwidth (3 dB): 900 MHz

• On-chip dither

• Analog Input buffer with high-impedance input

• Output options:

– Rx: decimate-by-2 and -4 options with

Low-Pass lFilter

– 200-MHz Complex bandwidth or 100-MHz real

bandwidth support

– DPD FB: 500 MSPS

• 1.9-VPP Differential full-scale input

• JESD204B interface:

– Subclass 1 support

– 1 Lane per ADC Up to 10 Gbps

– Dedicated SYNC pin for pair of channels

• Support for multi-chip synchronization

• 72-Pin VQFN package (10 mm × 10 mm)

• Key specifications:

– Power dissipation: 675 mW/ch

– Spectral performance (un-decimated)

• fIN = 190 MHz IF at –1 dBFS:

– SNR: 69.5 dBFS

– NSD: –153.5 dBFS/Hz

– SFDR: 86 dBc (HD2, HD3),

93 dBFS (Non HD2, HD3)

• fIN = 370 MHz IF at –3 dBFS:

– SNR: 68.5 dBFS

– NSD: –152.5 dBFS/Hz

– SFDR: 81 dBc (HD2, HD3),

86 dBFS (Non HD2, HD3)

2 Applications

• Radar and antenna arrays

• Broadband wireless and digitizers

• Cable CMTS, DOCSIS 3.1 receivers

• Communications test equipment

• Microwave receivers

• Software defined radio (SDR)

3 Description

The ADS54J66 is a low-power, wide-bandwidth,

14-bit, 500-MSPS, quad-channel, telecom receiver

device. The ADS54J66 supports a JESD204B serial

interface with data rates up to 10 Gbps with one

lane per channel. The buffered analog input provides

uniform input impedance across a wide frequency

range and minimizes sample-and-hold glitch energy.

The ADS54J66 provides excellent spurious-free

dynamic range (SFDR) over a large input frequency

range with very low power consumption. The digital

signal processing block includes complex mixers

followed by low-pass filters with decimate-by-2 and -4

options supporting up to 200-MHz receive bandwidth.

The JESD204B interface reduces the number of

interface lines, thus allowing high system integration

density. An internal phase-locked loop (PLL) multiplies

the incoming analog-to-digital converter (ADC)

sampling clock to derive the bit clock, which is used to

serialize the 14-bit data from each channel.