位置:74ALVCH16841DGGRG4.B > 74ALVCH16841DGGRG4.B详情
74ALVCH16841DGGRG4.B中文资料
74ALVCH16841DGGRG4.B数据手册规格书PDF详情
FEATURES
· Member of the Texas Instruments Widebus™
Family
· EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
· ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
· Latch-Up Performance Exceeds 250 mA Per
JESD 17
· Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
· Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DESCRIPTION
This 20-bit bus-interface D-type latch is designed for
1.65-V to 3.6-V VCC operation.
The SN74ALVCH16841 features 3-state outputs
designed specifically for driving highly capacitive or
relatively low-impedance loads. This device is
particularly suitable for implementing buffer registers,
unidirectional bus drivers, and working registers.
The SN74ALVCH16841 can be used as two 10-bit
latches or one 20-bit latch. The 20 latches are
transparent D-type latches. The device has
noninverting data (D) inputs and provides true data at
its outputs. While the latch-enable (1LE or 2LE) input
is high, the Q outputs of the corresponding 10-bit
latch follow the D inputs. When LE is taken low, the Q
outputs are latched at the levels set up at the D
inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16841 is characterized for operation from -40°C to 85°C.
| 供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
MICROCHIP/微芯 |
23+ |
SOT23-5 |
69820 |
终端可以免费供样,支持BOM配单! |
|||
Nexperia USA Inc. |
24+ |
56-TSSOP |
56200 |
一级代理/放心采购 |
|||
NEXPERIA/安世 |
2447 |
SOT364 |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
|||
NEXPERIA |
25+ |
SSOP-56 |
4854 |
就找我吧!--邀您体验愉快问购元件! |
|||
Nexperia(安世) |
2021+ |
TSSOP-56 |
499 |
||||
恩XP |
2021+ |
DHVQFN-20 |
7600 |
原装现货,欢迎询价 |
|||
恩XP |
24+ |
DHVQFN-20 |
30000 |
原装正品公司现货,假一赔十! |
|||
恩XP |
21+ |
DHVQFN-20 |
8080 |
只做原装,质量保证 |
|||
恩XP |
25+ |
DHVQFN-20 |
8880 |
原装认准芯泽盛世! |
|||
恩XP |
23+ |
DHVQFN-20 |
8080 |
正规渠道,只有原装! |
74ALVCH16841DGGRG4.B 资料下载更多...
74ALVCH16841DGGRG4.B 芯片相关型号
- CL03C050CA3GNN
- CL03C050CB31IN
- CL03C050DA31IN
- CL03C050DB31IN
- CL03C060DA3GNN
- CL03C060DA3GNW
- CL03C090CA3GNN
- CL03C090CA3GNW
- LQR2V392MSEG
- LQR2V392MSEH
- RK1206AS-R500XN-2Q
- RK1206AS-R500XN-2S
- RK1206AS-R500XN-81
- RK1206AS-R500XN-83
- S501T1BD
- S501T1CA
- S501T1CB
- S501T1CD
- S501T1DA
- S501T1DB
- S501T1DD
- S501T3AA
- S501T3AB
- S501T3AD
- S501T3BA
- S501T3BB
- S501T3BD
- S501T3CA
- S501T3CB
- SN74LVC1G99-Q1
Datasheet数据表PDF页码索引
- P1
- P2
- P3
- P4
- P5
- P6
- P7
- P8
- P9
- P10
- P11
- P12
- P13
- P14
- P15
- P16
- P17
- P18
- P19
- P20
- P21
- P22
- P23
- P24
- P25
- P26
- P27
- P28
- P29
- P30
- P31
- P32
- P33
- P34
- P35
- P36
- P37
- P38
- P39
- P40
- P41
- P42
- P43
- P44
- P45
- P46
- P47
- P48
- P49
- P50
- P51
- P52
- P53
- P54
- P55
- P56
- P57
- P58
- P59
- P60
- P61
- P62
- P63
- P64
- P65
- P66
- P67
- P68
- P69
- P70
- P71
- P72
- P73
- P74
- P75
- P76
- P77
- P78
- P79
- P80
- P81
- P82
- P83
- P84
- P85
- P86
- P87
- P88
- P89
- P90
- P91
- P92
- P93
- P94
- P95
- P96
- P97
- P98
- P99
- P100
- P101
- P102
- P103
- P104
- P105
- P106
- P107
