1 Features

• Wide operating range of 1.65 V to 5.5 V

• 5.5-V tolerant input pins

• LVxT enhanced inputs combined with open-drain

outputs provide maximum voltage translation

flexibility:

– Over 6.67-Mbps operation, (RPU = 1 kΩ,

CL = 30 pF)

– Up translation from 1.2 V to 5 V with 1.8-V

supply

– Down translation from 5 V to 0.8 V or even less

with any valid supply

• 5.5-V tolerant input pins

• Supports standard function pinout

• Latch-up performance exceeds 250 mA

per JESD 17

2 Applications

• Enable or disable a digital signal

• Controlling an indicator LED

• Translation between communication modules and

system controllers

3 Description

The SN74LV6T07 device contains six independent

buffers with open-drain outputs. Each buffer performs

the Boolean function Y = A in positive logic.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2 V input to 1.8 V output or 1.8 V input

to 3.3 V output). In addition, the 5-V tolerant input pins

enable down translation (for example, 3.3 V to 2.5 V

output).