位置:LMX1860PAP/EM > LMX1860PAP/EM详情

LMX1860PAP/EM中文资料

厂家型号

LMX1860PAP/EM

文件大小

2983.15Kbytes

页面数量

64

功能描述

LMX1860-SEP Low-Noise, High-Frequency JESD204B/C Buffer, Multiplier and Divider

数据手册

下载地址一下载地址二到原厂下载

生产厂商

TI1

LMX1860PAP/EM数据手册规格书PDF详情

1 Features

• VID #V62/24630

– Total ionizing dose 30krad (ELDRS-free)

– Single event latch-up (SEL) immune up to

43MeV - cm2 /mg

– Single event functional interrupt (SEFI) immune

up to 43MeV - cm2 /mg

• Clock buffer for 300MHz to 15GHz frequency

• Ultra-Low Noise

– Noise floor of –159dBc/Hz at 6GHz output

– 36-fs additive jitter (100Hz to fCLK) at 6GHz

output

– 5fs additive jitter (100Hz - 100MHz)

• 4 high-frequency clocks with corresponding

SYSREF outputs

– Shared divide by 1 (Buffer), 2, 3, 4, 5, 6, 7, and

8

– Shared programmable multiplier x2, x3, and x4

• Support pin mode options to configure the device

without SPI

• LOGICLK output with corresponding SYSREF

output

– On separate divide bank

– 1, 2, 4 pre-divider

– 1 (bypass), 2, …, 1023 post divider

• 8 programmable output power levels

• Synchronized SYSREF clock outputs

– 508 delay step adjustments of less than 2.5ps

each at 12.8GHz

– Generator and repeater modes

– Windowing feature for SYSREFREQ pins to

optimize timing

• SYNC feature to all divides and multiple devices

• 2.5V operating voltage

• –55ºC to 125ºC operating temperature

• High Reliability

– Controlled Baseline

– One Assembly/Test Site

– One Fabrication Site

– Extended Product Life Cycle

– Product Traceability

2 Applications

• Radar imaging payload

• Communications payloads

• Command and data handling

• Data converter clocking

• Clock distribution/multiplication/division

3 Description

The LMX1860-SEP is an buffer, divider and multiplier

that features high frequency, ultra-low jitter, and

SYSREF outputs. This device combined with an ultralow

noise reference clock source is an exemplary

design for clocking data converters, especially when

sampling above 3GHz. Each of the 4 high frequency

clock outputs and additional LOGICLK output is

paired with a SYSREF output clock signal. The

SYSREF signal for JESD interfaces can either be

internally generated or passed in as an input and

re-clocked to the device clocks. This device can

distribute the multichannel, low skew, ultra-low noise

local oscillator signals to multiple mixers by disabling

the SYSREF outputs.

更新时间:2025-10-10 18:30:00
供应商 型号 品牌 批号 封装 库存 备注 价格
TI(德州仪器)
2024+
N/A
500000
诚信服务,绝对原装原盘
NS
25+
SOP-14-3.9mm
3200
全新原装、诚信经营、公司现货销售!
ROHM/罗姆
23+
SOT663
50000
全新原装正品现货,支持订货
NS/美国国半
2450+
SMD
8850
只做原装正品假一赔十为客户做到零风险!!
25+
SOP
3200
绝对原装自家现货!真实库存!欢迎来电!
NS(GaAsTEK)
2023+
12388
NS
00/98+
SOP
1120
全新原装现货100真实自己公司
NS
23+
SOP16
7100
绝对全新原装!现货!特价!请放心订购!
NSC
25+
SOP16
1500
大量原装现货,特价甩卖!
NS
24+
SOP16
6980
原装现货,可开13%税票