1 Features

• ADC core:

– 12-Bit resolution

– Up to 1GSPS, 3GSPS, 5GSPS in singlechannel

mode

– Up to 500MSPS, 1.5GSPS, 2.5GSPS in dualchannel

mode

• Internal dither for low-magnitude, high-order

harmonics

• Low-latency LVDS interface:

– Total latency: < 10ns

– Up to 48 data pairs at 1.6Gbps

– Four DDR data clocks

– Strobe signals simplify synchronization

• Noise floor (no input, VFS = 1VPP-DIFF):

– Dual-channel mode: -143.5, -148,

-149.8dBFS/Hz

– Single-channel mode: -146.2, -150.3,

-152.2dBFS/Hz

• Buffered analog inputs with VCMI of 0V:

– Analog input bandwidth (–3dB): 8GHz

– Full-scale input voltage (VFS, default): 0.8VPP

• Noiseless aperture delay (TAD) adjustment:

– Precise sampling control: 19fs step

– Simplifies synchronization and interleaving

– Temperature and voltage invariant delays

• Easy-to-use synchronization features:

– Automatic SYSREF timing calibration

– Timestamp for sample marking

• Power consumption: 2.6, 2.8, 3W

2 Applications

• Oscilloscopes and digitizers

• Electronic Warfare (SIGINT, ELINT)

• Time-of-flight and LIDAR distance measurement

• Microwave backhaul

• Automotive radar testers

• Spectrometry

3 Description

The ADC12DL500, ADC12DL1500 and

ADC12DL2500 are a family of analog-to-digital

converters (ADC) that can sample up to 500MSPS,

1.5GSPS, and 2.5GSPS in dual-channel mode and

up to 1GSPS, 3GSPS, and 5GSPS in single-channel

mode. Programmable tradeoffs in channel count

(dual-channel mode) and sample rate (single-channel

mode) allow development of flexible hardware that

meets the needs of both high-channel count or wide

instantaneous signal bandwidth applications.

The devices uses a low-latency, low-voltage

differential signaling (LVDS) interface for latency

sensitive applications or when the simplicity of LVDS

is preferred. The interface uses up to 48 data

pairs, four double data rate (DDR) clocks, and

four strobe signals arranged in four 12-bit data

buses. The interface supports signaling rates of up

to 1.6Gbps. Strobe signals simplify synchronization

across buses and between multiple devices. The

strobe is generated internally and can be reset at

a deterministic time by the SYSREF input. Multidevice

synchronization is further eased by innovative

synchronization features such as noiseless aperture

delay (TAD) adjustment and SYSREF windowing.