TPS6200x High-Efficiency Step-Down Low Power DC-DC Converter

1 Features 1• High-Efficiency Synchronous Step-Down Converter with More than 95% Efficiency • 2-V to 5.5-V Operating Input Voltage Range • Adjustable Output Voltage Range From 0.8 V to VIN • Fixed Output Voltage Options Available in 0.9 V, 1 V, 1.2 V, 1.5 V, 1.8 V, 1.9 V, 2.5 V, and 3.3

1-pole/2-pole 16A polarized power relays Variety of contact arrangements

FEATURES 1. Variety of contact arrangements Wide lineup of 1 Form C, 1 Form A, 1 Form B, 2 Form C, 2 Form A, 2 Form B, 1 Form A 1 Form B. 2. Latching operation Latching via a polarized magnetic circuit structure allows remote operation and lower energy consumption 3. Compact with high c

Low Power 2 Output System Reset IC Series

Description The M62001 to M62008 are semiconductor integrated circuits whose optimum use is for the detection of the rise and fall in the power supply to a microcomputer system in order to reset or release the microcomputer system. Features • Bi-CMOS process realizes a configuration of low curr

LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES

DESCRIPTION The M62001~8 are semiconductor integrated circuits whose optimum use is for the detection of the rise and fall in the power supply to a microcomputer system in order to reset or release the microcomputer system. The M62001~8 carry out voltage detection in 2 steps and have 2 output pi

LOW POWER 2 OUTPUT SYSTEM RESET IC SERIES

DESCRIPTION The M62001~8 are semiconductor integrated circuits whose optimum use is for the detection of the rise and fall in the power supply to a microcomputer system in order to reset or release the microcomputer system. The M62001~8 carry out voltage detection in 2 steps and have 2 output pi

Low Power 2 Output System Reset IC Series

Description The M62001 to M62008 are semiconductor integrated circuits whose optimum use is for the detection of the rise and fall in the power supply to a microcomputer system in order to reset or release the microcomputer system. Features • Bi-CMOS process realizes a configuration of low curr