P-Channel Enhancement-Mode Vertical DMOS FETs

General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high inpu

P-Channel Enhancement-Mode Vertical DMOS FETs

Low Threshold DMOS Technology\nThese low threshold enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the h ❏ Low threshold — -2.4V max.\n❏ High input impedance\n❏ Low input capacitance — 95pF typical\n❏ Fast switching speeds\n❏ Low on resistance\n❏ Free from secondary breakdown\n❏ Low input and output leakage\n❏ Complementary N- and P-channel devicesApplications\n❏ Logic level interfaces – ideal for TTL ;

P-Channel Enhancement-Mode Vertical DMOS FETs

General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high inpu

N-Channel Enhancement-Mode Vertical DMOS FETs

Features ❏ Low threshold — 1.6V max. ❏ High input impedance ❏ Low input capacitance — 140pF typical ❏ Fast switching speeds ❏ Low on resistance ❏ Free from secondary breakdown ❏ Low input and output leakage ❏ Complementary N- and P-channel devices Applications ❏ Log

N-Channel Enhancement-Mode Vertical DMOS FETs

Features ❏ Low threshold — 1.6V max. ❏ High input impedance ❏ Low input capacitance — 140pF typical ❏ Fast switching speeds ❏ Low on resistance ❏ Free from secondary breakdown ❏ Low input and output leakage ❏ Complementary N- and P-channel devices Applications ❏ Log

SMD Power Inductors

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