Dual D-Type Flip Flop Preset and Clear

Features • High speed: fmax = 77 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 µA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28 VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays:

74HC CMOS logic IC series

CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear

文件：312.68 Kbytes Page：10 Pages

DUAL D-TYPE FLIP FLOP PRESET AND CLEAR

文件：236.41 Kbytes Page：6 Pages

Dual D-Type Flip Flop Preset and Clear

文件：234.14 Kbytes Page：9 Pages

Dual D-Type Flip Flop Preset and Clear

Features • High speed: fmax = 77 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 µA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28 VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays:

CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear

文件：312.68 Kbytes Page：10 Pages

DUAL D-TYPE FLIP FLOP PRESET AND CLEAR

文件：236.41 Kbytes Page：6 Pages

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

High Speed CMOS Logic

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Dual D-type flip-flop with set and reset; positive edge-trigger

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