DUAL 2-TO-4 LINE DECODER / DUAL 3-TO-8 LINE DECODER

The TC74HC155A is a high speed CMOS DUAL 2-to-4 LINE DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Features • High speed: tpd= 12 ns (typ.) at VCC= 5 V • Low pow

DUAL 2-TO-4 LINE DECODER / DUAL 3-TO-8 LINE DECODER

The TC74HC155A is a high speed CMOS DUAL 2-to-4 LINE DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Features • High speed: tpd= 12 ns (typ.) at VCC= 5 V • Low pow

DUAL 2-TO-4 LINE DECODER / DUAL 3-TO-8 LINE DECODER

The TC74HC155A is a high speed CMOS DUAL 2-to-4 LINE DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Features • High speed: tpd= 12 ns (typ.) at VCC= 5 V • Low pow

74HC CMOS logic IC series

Dual 2-to-4 Line Decoder 3-to-8 Line Decoder

文件：341.08 Kbytes Page：9 Pages

Dual 2-to-4 Line Decoder 3-to-8 Line Decoder

文件：341.08 Kbytes Page：9 Pages

74HC CMOS logic IC series

Dual 2-to-4 Line Decoder 3-to-8 Line Decoder

文件：341.08 Kbytes Page：9 Pages

Dual 2-to-4 Line Decoder 3-to-8 Line Decoder

文件：341.08 Kbytes Page：9 Pages

DUAL 2 TO 4 LINE DECODER 3 TO 8 LINE DECODER

DESCRIPTION The M54/74HC155 is a high speed CMOS DUAL 2-TO-4 LINE DECODER fabricated in silicon gate C2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED tPD = 12 ns (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA

Dual 2-to-4-line Decoders/Demultiplexers

Description This circuit features dual 1-line-to-4-line demultiplexer with individual strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each se

DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS

DUAL 2-TO-4 LINE DECODERS/DEMULTIPLEXERS

Dual 2-to-4-line Decoders/Demultiplexers

Description This circuit features dual 1-line-to-4-line demultiplexer with individual strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each sect

Dual 2-to-4-line Decoders/Demultiplexers

Description This circuit features dual 1-line-to-4-line demultiplexer with individual strobes and common binary-address input. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each se