3.3V/5V 2.5GHz PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL. The delay varies in discrete steps based on a control word presented to

3.3V/5V 2.5GHz PROGRAMMABLE DELAY

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3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

3.3V ECL Programmable Delay Chip

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3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages