3.3 V ECL 可编程延迟芯片

The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. Thedelay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure • Maximum Input Clock Frequency >1.2 GHz Typical\n• Programmable Range: 0 ns to 10 ns\n• Delay Range: 2.2 ns to 12.2 ns\n• 10 ps Increments\n• PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V\n• NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V\n• IN/INb Inputs Accept LVPECL;

3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：147.17 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：147.17 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages

封装/外壳：32-LQFP 功能：可编程 包装：卷带（TR） 描述：IC DELAY LN 1024TAP PROG 32LQFP 集成电路（IC） 延迟线

3.3V ECL Programmable Delay Chip

文件：147.17 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：147.17 Kbytes Page：17 Pages

封装/外壳：32-VFQFN 裸露焊盘 功能：可编程 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC DELAY LINE 1024TAP PROG 32QFN 集成电路（IC） 延迟线

3.3V ECL Programmable Delay Chip

文件：147.17 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

文件：189.11 Kbytes Page：17 Pages

3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

3.3V/5V 2.5GHz PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL. The delay varies in discrete steps based on a control word presented to

3.3V/5V 2.5GHz PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL. The delay varies in discrete steps based on a control word presented to

3.3V/5V 2.5GHz PROGRAMMABLE DELAY CHIP

DESCRIPTION The SY100EP195V is a programmable delay line, varying the time a logic signal takes to traverse from IN to Q. This delay can vary from about 2.2ns to about 12.2ns. The input can be PECL, LVPECL, NECL, or LVNECL. The delay varies in discrete steps based on a control word presented to