Ultra low on-resistance

Description These devices utilize the 7th generation of design rules of ST’s proprietary STripFET™ technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest R DS(on) in all packages. Features • Ultra low on-resistance • 100 avalanche tested Applications • Switchin

N沟道100 V、0.027 Ohm典型值、25 A STripFET F7功率MOSFET，DPAK封装

该器件使用ST专有的STripFET™技术的第七代设计规则，具有新的栅极结构。因而，功率MOSFET在不同封装中都能呈现最低的RDS（on）。 • 超低导通电阻 \n• 经过100％雪崩测试;

N-Channel 100-V (D-S) MOSFET

文件：985 Kbytes Page：8 Pages

丝印代码：DPAK；isc N-Channel MOSFET Transistor

文件：323.93 Kbytes Page：2 Pages

Ultra low on-resistance

Description These devices utilize the 7th generation of design rules of ST’s proprietary STripFET™ technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest R DS(on) in all packages. Features • Ultra low on-resistance • 100 avalanche tested Applications • Switchin

Ultra low on-resistance

Description These devices utilize the 7th generation of design rules of ST’s proprietary STripFET™ technology, with a new gate structure. The resulting Power MOSFET exhibits the lowest R DS(on) in all packages. Features • Ultra low on-resistance • 100 avalanche tested Applications • Switchin

isc N-Channel MOSFET Transistor

文件：310.99 Kbytes Page：2 Pages